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fix: pass remaining riscv isa tests

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This commit is contained in:
abnerhexu
2026-06-27 07:07:07 +00:00
parent a2e0126199
commit a32db39c80
38 changed files with 81187 additions and 19321 deletions
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8
src/main/scala/frontend/ICache.scala
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@@ -14,6 +14,7 @@ class ICache(p: CoreParams = CoreParams()) extends Module {
val reqAddr = Input(UInt(p.xlen.W))
val reqPc = Input(UInt(p.xlen.W))
val flush = Input(Bool())
val invalidate = Input(Bool())
val respReady = Input(Bool())
val memReqValid = Output(Bool())
val memReqAddr = Output(UInt(p.xlen.W))
@@ -102,7 +103,12 @@ class ICache(p: CoreParams = CoreParams()) extends Module {
Mux(state === sMiss && io.memRespValid, missResp, lookupResp))
io.miss := state === sLookup && !hit || state === sMiss
when(io.flush) {
when(io.invalidate) {
valid := VecInit(Seq.fill(sets)(VecInit(Seq.fill(p.iCacheWays)(
VecInit(Seq.fill(lineInsts)(false.B))))))
state := sIdle
missReqSent := false.B
}.elsewhen(io.flush) {
state := sIdle
missReqSent := false.B
}.elsewhen(state === sIdle) {