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fix: pass remaining riscv isa tests

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This commit is contained in:
abnerhexu
2026-06-27 07:07:07 +00:00
parent a2e0126199
commit a32db39c80
38 changed files with 81187 additions and 19321 deletions
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7
src/main/scala/decode/Decoder.scala
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@@ -30,6 +30,7 @@ class Decoder(p: CoreParams = CoreParams()) extends Module {
d.rd := rd
d.funct3 := funct3
d.funct7 := funct7
d.amoOp := io.inst(31, 27)
d.immI := immI
d.immS := immS
d.immB := immB
@@ -106,6 +107,9 @@ class Decoder(p: CoreParams = CoreParams()) extends Module {
d.opClass := Consts.OP_ALU
d.aluFn := Mux(funct7 === "b0000001".U, MuxLookup(funct3, Consts.ALU_MUL)(Seq(
"b000".U -> Consts.ALU_MUL,
"b001".U -> Consts.ALU_MULH,
"b010".U -> Consts.ALU_MULHSU,
"b011".U -> Consts.ALU_MULHU,
"b100".U -> Consts.ALU_DIV,
"b101".U -> Consts.ALU_DIVU,
"b110".U -> Consts.ALU_REM,
@@ -123,6 +127,7 @@ class Decoder(p: CoreParams = CoreParams()) extends Module {
}
is("b0001111".U) {
d.opClass := Consts.OP_SYSTEM
d.isFenceI := funct3 === "b001".U
}
is("b1110011".U) {
d.isSystem := true.B
@@ -131,7 +136,7 @@ class Decoder(p: CoreParams = CoreParams()) extends Module {
}
is("b0101111".U) {
d.isLoad := true.B
d.isStore := true.B
d.isAmo := true.B
d.writesRd := rd =/= 0.U
d.memWidth := Mux(funct3 === "b010".U, 2.U, 3.U)
d.opClass := Consts.OP_LOAD