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fix: pass remaining riscv isa tests

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This commit is contained in:
abnerhexu
2026-06-27 07:07:07 +00:00
parent a2e0126199
commit a32db39c80
38 changed files with 81187 additions and 19321 deletions
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5
sim/verilator/testbench.cpp
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@@ -64,6 +64,7 @@ int main(int argc, char** argv) {
fprintf(stderr, "Failed to load test binary\n");
return 1;
}
uint64_t tohost_addr = mem->get_tohost_addr();
// Reset
core->reset = 1;
@@ -102,7 +103,7 @@ int main(int argc, char** argv) {
// Handle data memory interface
if (core->io_dmem_req_valid) {
uint64_t addr = core->io_dmem_req_bits_addr;
if ((addr < MEM_BASE || addr >= MEM_BASE + MEM_SIZE) && addr != TOHOST_ADDR && bad_access_reports < 32) {
if ((addr < MEM_BASE || addr >= MEM_BASE + MEM_SIZE) && addr != tohost_addr && bad_access_reports < 32) {
fprintf(stderr,
"[%lu] Bad dmem %s addr=0x%lx data=0x%lx size=%u\n",
cycle,
@@ -114,7 +115,7 @@ int main(int argc, char** argv) {
}
// Check for tohost write
if (core->io_dmem_req_bits_isStore && addr == TOHOST_ADDR) {
if (core->io_dmem_req_bits_isStore && addr == tohost_addr) {
saw_tohost_req = true;
uint64_t tohost = core->io_dmem_req_bits_data;
if (tohost == 1) {