fix: pass remaining riscv isa tests

sim/verilator/memory.cpp

@@ -5,8 +5,9 @@
 #include <fcntl.h>
 #include <unistd.h>
 #include <sys/stat.h>
+#include <vector>
 
-Memory::Memory() : base_addr(MEM_BASE), entry_point(MEM_BASE) {
+Memory::Memory() : base_addr(MEM_BASE), entry_point(MEM_BASE), tohost_addr(TOHOST_ADDR) {
     mem.resize(MEM_SIZE, 0);
 }
 
@@ -105,6 +106,44 @@ bool Memory::load_elf(const std::string& filename) {
         }
     }
 
+    if (ehdr.e_shoff != 0 && ehdr.e_shnum != 0) {
+        std::vector<Elf64_Shdr> shdrs(ehdr.e_shnum);
+        lseek(fd, ehdr.e_shoff, SEEK_SET);
+        if (read(fd, shdrs.data(), ehdr.e_shnum * sizeof(Elf64_Shdr)) == (ssize_t)(ehdr.e_shnum * sizeof(Elf64_Shdr))) {
+            for (int i = 0; i < ehdr.e_shnum; i++) {
+                const Elf64_Shdr& symtab = shdrs[i];
+                if (symtab.sh_type != SHT_SYMTAB || symtab.sh_entsize == 0 ||
+                    symtab.sh_link >= ehdr.e_shnum) {
+                    continue;
+                }
+
+                const Elf64_Shdr& strtab = shdrs[symtab.sh_link];
+                std::vector<char> strings(strtab.sh_size);
+                lseek(fd, strtab.sh_offset, SEEK_SET);
+                if (read(fd, strings.data(), strtab.sh_size) != (ssize_t)strtab.sh_size) {
+                    continue;
+                }
+
+                size_t nsyms = symtab.sh_size / symtab.sh_entsize;
+                std::vector<Elf64_Sym> symbols(nsyms);
+                lseek(fd, symtab.sh_offset, SEEK_SET);
+                if (read(fd, symbols.data(), symtab.sh_size) != (ssize_t)symtab.sh_size) {
+                    continue;
+                }
+
+                for (const Elf64_Sym& sym : symbols) {
+                    if (sym.st_name >= strings.size()) {
+                        continue;
+                    }
+                    if (strcmp(&strings[sym.st_name], "tohost") == 0) {
+                        tohost_addr = sym.st_value;
+                        break;
+                    }
+                }
+            }
+        }
+    }
+
     close(fd);
     printf("ELF loaded: entry=0x%lx\n", entry_point);
     return true;

sim/verilator/memory.h

@@ -31,9 +31,11 @@ public:
     void write64(uint64_t addr, uint64_t data);
 
     uint64_t get_entry_point() const { return entry_point; }
+    uint64_t get_tohost_addr() const { return tohost_addr; }
 
 private:
     uint64_t entry_point;
+    uint64_t tohost_addr;
     uint64_t to_offset(uint64_t addr);
 };
 

sim/verilator/testbench.cpp

@@ -64,6 +64,7 @@ int main(int argc, char** argv) {
         fprintf(stderr, "Failed to load test binary\n");
         return 1;
     }
+    uint64_t tohost_addr = mem->get_tohost_addr();
 
     // Reset
     core->reset = 1;
@@ -102,7 +103,7 @@ int main(int argc, char** argv) {
         // Handle data memory interface
         if (core->io_dmem_req_valid) {
             uint64_t addr = core->io_dmem_req_bits_addr;
-            if ((addr < MEM_BASE || addr >= MEM_BASE + MEM_SIZE) && addr != TOHOST_ADDR && bad_access_reports < 32) {
+            if ((addr < MEM_BASE || addr >= MEM_BASE + MEM_SIZE) && addr != tohost_addr && bad_access_reports < 32) {
                 fprintf(stderr,
                         "[%lu] Bad dmem %s addr=0x%lx data=0x%lx size=%u\n",
                         cycle,
@@ -114,7 +115,7 @@ int main(int argc, char** argv) {
             }
 
             // Check for tohost write
-            if (core->io_dmem_req_bits_isStore && addr == TOHOST_ADDR) {
+            if (core->io_dmem_req_bits_isStore && addr == tohost_addr) {
                 saw_tohost_req = true;
                 uint64_t tohost = core->io_dmem_req_bits_data;
                 if (tohost == 1) {