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fix: pass remaining riscv isa tests

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This commit is contained in:
abnerhexu
2026-06-27 07:07:07 +00:00
parent a2e0126199
commit a32db39c80
38 changed files with 81187 additions and 19321 deletions
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66
generated-ooo/RenameStage.sv
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@@ -18,7 +18,8 @@ module RenameStage(
input [3:0] io_in_0_opClass,
input [4:0] io_in_0_aluFn,
input [2:0] io_in_0_memWidth,
input io_in_0_isLoad,
input io_in_0_memSigned,
io_in_0_isLoad,
io_in_0_isStore,
io_in_0_isBranch,
io_in_0_isJal,
@@ -28,7 +29,10 @@ module RenameStage(
io_in_0_isOpImm,
io_in_0_isWord,
io_in_0_isSystem,
io_in_0_writesRd,
io_in_0_isFenceI,
io_in_0_isAmo,
input [4:0] io_in_0_amoOp,
input io_in_0_writesRd,
io_in_0_illegal,
input [63:0] io_in_1_pc,
input [31:0] io_in_1_inst,
@@ -44,7 +48,8 @@ module RenameStage(
input [3:0] io_in_1_opClass,
input [4:0] io_in_1_aluFn,
input [2:0] io_in_1_memWidth,
input io_in_1_isLoad,
input io_in_1_memSigned,
io_in_1_isLoad,
io_in_1_isStore,
io_in_1_isBranch,
io_in_1_isJal,
@@ -54,7 +59,10 @@ module RenameStage(
io_in_1_isOpImm,
io_in_1_isWord,
io_in_1_isSystem,
io_in_1_writesRd,
io_in_1_isFenceI,
io_in_1_isAmo,
input [4:0] io_in_1_amoOp,
input io_in_1_writesRd,
io_in_1_illegal,
output io_outValid_0,
io_outValid_1,
@@ -70,7 +78,8 @@ module RenameStage(
io_out_0_decoded_immJ,
output [4:0] io_out_0_decoded_aluFn,
output [2:0] io_out_0_decoded_memWidth,
output io_out_0_decoded_isLoad,
output io_out_0_decoded_memSigned,
io_out_0_decoded_isLoad,
io_out_0_decoded_isStore,
io_out_0_decoded_isBranch,
io_out_0_decoded_isJal,
@@ -80,7 +89,10 @@ module RenameStage(
io_out_0_decoded_isOpImm,
io_out_0_decoded_isWord,
io_out_0_decoded_isSystem,
io_out_0_decoded_writesRd,
io_out_0_decoded_isFenceI,
io_out_0_decoded_isAmo,
output [4:0] io_out_0_decoded_amoOp,
output io_out_0_decoded_writesRd,
io_out_0_decoded_illegal,
output [5:0] io_out_0_prs1,
io_out_0_prs2,
@@ -100,7 +112,8 @@ module RenameStage(
io_out_1_decoded_immJ,
output [4:0] io_out_1_decoded_aluFn,
output [2:0] io_out_1_decoded_memWidth,
output io_out_1_decoded_isLoad,
output io_out_1_decoded_memSigned,
io_out_1_decoded_isLoad,
io_out_1_decoded_isStore,
io_out_1_decoded_isBranch,
io_out_1_decoded_isJal,
@@ -110,7 +123,10 @@ module RenameStage(
io_out_1_decoded_isOpImm,
io_out_1_decoded_isWord,
io_out_1_decoded_isSystem,
io_out_1_decoded_writesRd,
io_out_1_decoded_isFenceI,
io_out_1_decoded_isAmo,
output [4:0] io_out_1_decoded_amoOp,
output io_out_1_decoded_writesRd,
io_out_1_decoded_illegal,
output [5:0] io_out_1_prs1,
io_out_1_prs2,
@@ -167,6 +183,7 @@ module RenameStage(
output [2:0] io_commitEntry_0_csrCmd,
output [63:0] io_commitEntry_0_csrRs1,
output [4:0] io_commitEntry_0_csrZimm,
output io_commitEntry_0_fenceI,
output [5:0] io_commitEntry_1_robIdx,
output [4:0] io_commitEntry_1_archDest,
output io_commitEntry_1_writesDest,
@@ -183,6 +200,7 @@ module RenameStage(
output [2:0] io_commitEntry_1_csrCmd,
output [63:0] io_commitEntry_1_csrRs1,
output [4:0] io_commitEntry_1_csrZimm,
output io_commitEntry_1_fenceI,
input io_commitMapValid_0,
io_commitMapValid_1,
input [4:0] io_commitArch_0,
@@ -880,11 +898,13 @@ module RenameStage(
.io_allocateEntry_0_opClass (io_in_0_opClass),
.io_allocateEntry_0_dest (e_dest),
.io_allocateEntry_0_oldDest (_table_io_oldPrd_0),
.io_allocateEntry_0_fenceI (io_in_0_isFenceI),
.io_allocateEntry_1_archDest (io_in_1_rd),
.io_allocateEntry_1_writesDest (io_in_1_writesRd),
.io_allocateEntry_1_opClass (io_in_1_opClass),
.io_allocateEntry_1_dest (e_1_dest),
.io_allocateEntry_1_oldDest (_table_io_oldPrd_1),
.io_allocateEntry_1_fenceI (io_in_1_isFenceI),
.io_allocateIdx_0 (io_out_0_robIdx),
.io_allocateIdx_1 (io_out_1_robIdx),
.io_canAllocate (_rob_io_canAllocate),
@@ -930,6 +950,7 @@ module RenameStage(
.io_commit_0_csrCmd (io_commitEntry_0_csrCmd),
.io_commit_0_csrRs1 (io_commitEntry_0_csrRs1),
.io_commit_0_csrZimm (io_commitEntry_0_csrZimm),
.io_commit_0_fenceI (io_commitEntry_0_fenceI),
.io_commit_1_robIdx (io_commitEntry_1_robIdx),
.io_commit_1_archDest (io_commitEntry_1_archDest),
.io_commit_1_writesDest (io_commitEntry_1_writesDest),
@@ -946,6 +967,7 @@ module RenameStage(
.io_commit_1_csrCmd (io_commitEntry_1_csrCmd),
.io_commit_1_csrRs1 (io_commitEntry_1_csrRs1),
.io_commit_1_csrZimm (io_commitEntry_1_csrZimm),
.io_commit_1_fenceI (io_commitEntry_1_fenceI),
.io_commitReady_0 (io_commitReady_0),
.io_commitReady_1 (io_commitReady_1),
.io_flush (io_flush)
@@ -964,6 +986,7 @@ module RenameStage(
assign io_out_0_decoded_immJ = io_in_0_immJ;
assign io_out_0_decoded_aluFn = io_in_0_aluFn;
assign io_out_0_decoded_memWidth = io_in_0_memWidth;
assign io_out_0_decoded_memSigned = io_in_0_memSigned;
assign io_out_0_decoded_isLoad = io_in_0_isLoad;
assign io_out_0_decoded_isStore = io_in_0_isStore;
assign io_out_0_decoded_isBranch = io_in_0_isBranch;
@@ -974,12 +997,23 @@ module RenameStage(
assign io_out_0_decoded_isOpImm = io_in_0_isOpImm;
assign io_out_0_decoded_isWord = io_in_0_isWord;
assign io_out_0_decoded_isSystem = io_in_0_isSystem;
assign io_out_0_decoded_isFenceI = io_in_0_isFenceI;
assign io_out_0_decoded_isAmo = io_in_0_isAmo;
assign io_out_0_decoded_amoOp = io_in_0_amoOp;
assign io_out_0_decoded_writesRd = io_in_0_writesRd;
assign io_out_0_decoded_illegal = io_in_0_illegal;
assign io_out_0_prs1 = _table_io_prs1_0;
assign io_out_0_prs2 = _table_io_prs2_0;
assign io_out_0_src1Ready = io_in_0_rs1 == 5'h0 | _GEN[_table_io_prs1_0];
assign io_out_0_src2Ready = io_in_0_rs2 == 5'h0 | _GEN[_table_io_prs2_0];
assign io_out_0_src1Ready =
|{io_in_0_rs1 == 5'h0,
_GEN[_table_io_prs1_0],
io_wbValid_1 & io_wbPhys_1 == _table_io_prs1_0,
io_wbValid_0 & io_wbPhys_0 == _table_io_prs1_0};
assign io_out_0_src2Ready =
|{io_in_0_rs2 == 5'h0,
_GEN[_table_io_prs2_0],
io_wbValid_1 & io_wbPhys_1 == _table_io_prs2_0,
io_wbValid_0 & io_wbPhys_0 == _table_io_prs2_0};
assign io_out_0_prd = e_dest;
assign io_out_1_decoded_pc = io_in_1_pc;
assign io_out_1_decoded_inst = io_in_1_inst;
@@ -993,6 +1027,7 @@ module RenameStage(
assign io_out_1_decoded_immJ = io_in_1_immJ;
assign io_out_1_decoded_aluFn = io_in_1_aluFn;
assign io_out_1_decoded_memWidth = io_in_1_memWidth;
assign io_out_1_decoded_memSigned = io_in_1_memSigned;
assign io_out_1_decoded_isLoad = io_in_1_isLoad;
assign io_out_1_decoded_isStore = io_in_1_isStore;
assign io_out_1_decoded_isBranch = io_in_1_isBranch;
@@ -1003,16 +1038,23 @@ module RenameStage(
assign io_out_1_decoded_isOpImm = io_in_1_isOpImm;
assign io_out_1_decoded_isWord = io_in_1_isWord;
assign io_out_1_decoded_isSystem = io_in_1_isSystem;
assign io_out_1_decoded_isFenceI = io_in_1_isFenceI;
assign io_out_1_decoded_isAmo = io_in_1_isAmo;
assign io_out_1_decoded_amoOp = io_in_1_amoOp;
assign io_out_1_decoded_writesRd = io_in_1_writesRd;
assign io_out_1_decoded_illegal = io_in_1_illegal;
assign io_out_1_prs1 = _table_io_prs1_1;
assign io_out_1_prs2 = _table_io_prs2_1;
assign io_out_1_src1Ready =
io_in_1_rs1 == 5'h0 | ~(table_io_wen_0 & (|io_in_0_rd) & io_in_0_rd == io_in_1_rs1)
& _GEN[_table_io_prs1_1];
& (|{_GEN[_table_io_prs1_1],
io_wbValid_1 & io_wbPhys_1 == _table_io_prs1_1,
io_wbValid_0 & io_wbPhys_0 == _table_io_prs1_1});
assign io_out_1_src2Ready =
io_in_1_rs2 == 5'h0 | ~(table_io_wen_0 & (|io_in_0_rd) & io_in_0_rd == io_in_1_rs2)
& _GEN[_table_io_prs2_1];
& (|{_GEN[_table_io_prs2_1],
io_wbValid_1 & io_wbPhys_1 == _table_io_prs2_1,
io_wbValid_0 & io_wbPhys_0 == _table_io_prs2_1});
assign io_out_1_prd = e_1_dest;
assign io_canAccept = {1'h0, io_inValid_0} + {1'h0, io_inValid_1} == 2'h0 | canRename;
endmodule