fix: pass remaining riscv isa tests
This commit is contained in:
@@ -18,7 +18,8 @@ module OoOBackend(
|
||||
input [3:0] io_decode_0_opClass,
|
||||
input [4:0] io_decode_0_aluFn,
|
||||
input [2:0] io_decode_0_memWidth,
|
||||
input io_decode_0_isLoad,
|
||||
input io_decode_0_memSigned,
|
||||
io_decode_0_isLoad,
|
||||
io_decode_0_isStore,
|
||||
io_decode_0_isBranch,
|
||||
io_decode_0_isJal,
|
||||
@@ -28,7 +29,10 @@ module OoOBackend(
|
||||
io_decode_0_isOpImm,
|
||||
io_decode_0_isWord,
|
||||
io_decode_0_isSystem,
|
||||
io_decode_0_writesRd,
|
||||
io_decode_0_isFenceI,
|
||||
io_decode_0_isAmo,
|
||||
input [4:0] io_decode_0_amoOp,
|
||||
input io_decode_0_writesRd,
|
||||
io_decode_0_illegal,
|
||||
input [63:0] io_decode_1_pc,
|
||||
input [31:0] io_decode_1_inst,
|
||||
@@ -44,7 +48,8 @@ module OoOBackend(
|
||||
input [3:0] io_decode_1_opClass,
|
||||
input [4:0] io_decode_1_aluFn,
|
||||
input [2:0] io_decode_1_memWidth,
|
||||
input io_decode_1_isLoad,
|
||||
input io_decode_1_memSigned,
|
||||
io_decode_1_isLoad,
|
||||
io_decode_1_isStore,
|
||||
io_decode_1_isBranch,
|
||||
io_decode_1_isJal,
|
||||
@@ -54,12 +59,16 @@ module OoOBackend(
|
||||
io_decode_1_isOpImm,
|
||||
io_decode_1_isWord,
|
||||
io_decode_1_isSystem,
|
||||
io_decode_1_writesRd,
|
||||
io_decode_1_isFenceI,
|
||||
io_decode_1_isAmo,
|
||||
input [4:0] io_decode_1_amoOp,
|
||||
input io_decode_1_writesRd,
|
||||
io_decode_1_illegal,
|
||||
output io_decodeReady,
|
||||
io_flush,
|
||||
output [63:0] io_redirectPc,
|
||||
output io_dmemReqValid,
|
||||
output io_invalidateICache,
|
||||
io_dmemReqValid,
|
||||
output [63:0] io_dmemReq_addr,
|
||||
io_dmemReq_data,
|
||||
output io_dmemReq_isStore,
|
||||
@@ -78,6 +87,9 @@ module OoOBackend(
|
||||
wire _lsu_io_pageFault;
|
||||
wire [3:0] _sq_io_enqIdx;
|
||||
wire _sq_io_forwardValid;
|
||||
wire [63:0] _sq_io_forwardData;
|
||||
wire _sq_io_forwardBlock;
|
||||
wire _sq_io_olderStoreValid;
|
||||
wire _sq_io_drainValid;
|
||||
wire [63:0] _sq_io_drain_addr;
|
||||
wire [63:0] _sq_io_drain_data;
|
||||
@@ -132,6 +144,7 @@ module OoOBackend(
|
||||
wire [63:0] _issue_io_out_0_decoded_immJ;
|
||||
wire [4:0] _issue_io_out_0_decoded_aluFn;
|
||||
wire [2:0] _issue_io_out_0_decoded_memWidth;
|
||||
wire _issue_io_out_0_decoded_memSigned;
|
||||
wire _issue_io_out_0_decoded_isLoad;
|
||||
wire _issue_io_out_0_decoded_isStore;
|
||||
wire _issue_io_out_0_decoded_isBranch;
|
||||
@@ -142,6 +155,9 @@ module OoOBackend(
|
||||
wire _issue_io_out_0_decoded_isOpImm;
|
||||
wire _issue_io_out_0_decoded_isWord;
|
||||
wire _issue_io_out_0_decoded_isSystem;
|
||||
wire _issue_io_out_0_decoded_isFenceI;
|
||||
wire _issue_io_out_0_decoded_isAmo;
|
||||
wire [4:0] _issue_io_out_0_decoded_amoOp;
|
||||
wire _issue_io_out_0_decoded_writesRd;
|
||||
wire _issue_io_out_0_decoded_illegal;
|
||||
wire [5:0] _issue_io_out_0_prs1;
|
||||
@@ -159,6 +175,7 @@ module OoOBackend(
|
||||
wire [63:0] _issue_io_out_1_decoded_immJ;
|
||||
wire [4:0] _issue_io_out_1_decoded_aluFn;
|
||||
wire [2:0] _issue_io_out_1_decoded_memWidth;
|
||||
wire _issue_io_out_1_decoded_memSigned;
|
||||
wire _issue_io_out_1_decoded_isLoad;
|
||||
wire _issue_io_out_1_decoded_isStore;
|
||||
wire _issue_io_out_1_decoded_isBranch;
|
||||
@@ -169,6 +186,9 @@ module OoOBackend(
|
||||
wire _issue_io_out_1_decoded_isOpImm;
|
||||
wire _issue_io_out_1_decoded_isWord;
|
||||
wire _issue_io_out_1_decoded_isSystem;
|
||||
wire _issue_io_out_1_decoded_isFenceI;
|
||||
wire _issue_io_out_1_decoded_isAmo;
|
||||
wire [4:0] _issue_io_out_1_decoded_amoOp;
|
||||
wire _issue_io_out_1_decoded_writesRd;
|
||||
wire _issue_io_out_1_decoded_illegal;
|
||||
wire [5:0] _issue_io_out_1_prs1;
|
||||
@@ -189,6 +209,7 @@ module OoOBackend(
|
||||
wire [63:0] _rename_io_out_0_decoded_immJ;
|
||||
wire [4:0] _rename_io_out_0_decoded_aluFn;
|
||||
wire [2:0] _rename_io_out_0_decoded_memWidth;
|
||||
wire _rename_io_out_0_decoded_memSigned;
|
||||
wire _rename_io_out_0_decoded_isLoad;
|
||||
wire _rename_io_out_0_decoded_isStore;
|
||||
wire _rename_io_out_0_decoded_isBranch;
|
||||
@@ -199,6 +220,9 @@ module OoOBackend(
|
||||
wire _rename_io_out_0_decoded_isOpImm;
|
||||
wire _rename_io_out_0_decoded_isWord;
|
||||
wire _rename_io_out_0_decoded_isSystem;
|
||||
wire _rename_io_out_0_decoded_isFenceI;
|
||||
wire _rename_io_out_0_decoded_isAmo;
|
||||
wire [4:0] _rename_io_out_0_decoded_amoOp;
|
||||
wire _rename_io_out_0_decoded_writesRd;
|
||||
wire _rename_io_out_0_decoded_illegal;
|
||||
wire [5:0] _rename_io_out_0_prs1;
|
||||
@@ -219,6 +243,7 @@ module OoOBackend(
|
||||
wire [63:0] _rename_io_out_1_decoded_immJ;
|
||||
wire [4:0] _rename_io_out_1_decoded_aluFn;
|
||||
wire [2:0] _rename_io_out_1_decoded_memWidth;
|
||||
wire _rename_io_out_1_decoded_memSigned;
|
||||
wire _rename_io_out_1_decoded_isLoad;
|
||||
wire _rename_io_out_1_decoded_isStore;
|
||||
wire _rename_io_out_1_decoded_isBranch;
|
||||
@@ -229,6 +254,9 @@ module OoOBackend(
|
||||
wire _rename_io_out_1_decoded_isOpImm;
|
||||
wire _rename_io_out_1_decoded_isWord;
|
||||
wire _rename_io_out_1_decoded_isSystem;
|
||||
wire _rename_io_out_1_decoded_isFenceI;
|
||||
wire _rename_io_out_1_decoded_isAmo;
|
||||
wire [4:0] _rename_io_out_1_decoded_amoOp;
|
||||
wire _rename_io_out_1_decoded_writesRd;
|
||||
wire _rename_io_out_1_decoded_illegal;
|
||||
wire [5:0] _rename_io_out_1_prs1;
|
||||
@@ -256,6 +284,7 @@ module OoOBackend(
|
||||
wire [2:0] _rename_io_commitEntry_0_csrCmd;
|
||||
wire [63:0] _rename_io_commitEntry_0_csrRs1;
|
||||
wire [4:0] _rename_io_commitEntry_0_csrZimm;
|
||||
wire _rename_io_commitEntry_0_fenceI;
|
||||
wire [5:0] _rename_io_commitEntry_1_robIdx;
|
||||
wire [4:0] _rename_io_commitEntry_1_archDest;
|
||||
wire _rename_io_commitEntry_1_writesDest;
|
||||
@@ -272,6 +301,7 @@ module OoOBackend(
|
||||
wire [2:0] _rename_io_commitEntry_1_csrCmd;
|
||||
wire [63:0] _rename_io_commitEntry_1_csrRs1;
|
||||
wire [4:0] _rename_io_commitEntry_1_csrZimm;
|
||||
wire _rename_io_commitEntry_1_fenceI;
|
||||
reg wakeupReg_0_valid;
|
||||
reg [5:0] wakeupReg_0_phys;
|
||||
reg wakeupReg_1_valid;
|
||||
@@ -280,87 +310,135 @@ module OoOBackend(
|
||||
reg [5:0] loadPendingRob;
|
||||
reg [5:0] loadPendingPhys;
|
||||
reg [3:0] loadPendingLq;
|
||||
wire loadRespValid = _lsu_io_respValid & loadPending;
|
||||
reg forwardPending;
|
||||
reg [5:0] forwardPendingRob;
|
||||
reg [5:0] forwardPendingPhys;
|
||||
reg [3:0] forwardPendingLq;
|
||||
reg [63:0] forwardPendingData;
|
||||
wire loadRespValid = _lsu_io_respValid & loadPending | forwardPending;
|
||||
wire isMem0 = _issue_io_out_0_decoded_isLoad | _issue_io_out_0_decoded_isStore;
|
||||
wire memIssue_0 = _issue_io_outValid_0 & isMem0;
|
||||
wire isMem1 = _issue_io_out_1_decoded_isLoad | _issue_io_out_1_decoded_isStore;
|
||||
wire csrReadReq_0 =
|
||||
_issue_io_outValid_0 & _issue_io_out_0_decoded_isSystem
|
||||
& (|_issue_io_out_0_decoded_funct3);
|
||||
wire _memReady1_T_1 = _lsu_io_reqReady & ~loadPending;
|
||||
wire issue_io_outReady_0 = ~isMem0 | _memReady1_T_1;
|
||||
wire _amoBlocked1_T = _sq_io_olderStoreValid | _sq_io_drainValid;
|
||||
wire _memReady1_T_1 = _lsu_io_reqReady & ~loadPending & ~forwardPending;
|
||||
wire issue_io_outReady_0 =
|
||||
(~isMem0 | _memReady1_T_1 & ~(_issue_io_out_0_decoded_isAmo & _amoBlocked1_T)
|
||||
& ~(_issue_io_out_0_decoded_isLoad & _sq_io_forwardBlock)) & ~loadPending
|
||||
& ~forwardPending;
|
||||
wire issue_io_outReady_1 =
|
||||
(~isMem1 | _memReady1_T_1 & ~memIssue_0)
|
||||
(~isMem1 | _memReady1_T_1 & ~memIssue_0
|
||||
& ~(_issue_io_out_1_decoded_isAmo & _amoBlocked1_T)
|
||||
& ~(_issue_io_out_1_decoded_isLoad & _sq_io_forwardBlock))
|
||||
& ~(csrReadReq_0 & _issue_io_outValid_1 & _issue_io_out_1_decoded_isSystem
|
||||
& (|_issue_io_out_1_decoded_funct3));
|
||||
wire issueFire_0 = _issue_io_outValid_0 & issue_io_outReady_0;
|
||||
wire issueFire_1 = _issue_io_outValid_1 & issue_io_outReady_1;
|
||||
wire [63:0] memSrc2 = memIssue_0 ? _prf_io_rdata_1 : _prf_io_rdata_3;
|
||||
wire [2:0] sq_io_size =
|
||||
memIssue_0 ? _issue_io_out_0_decoded_memWidth : _issue_io_out_1_decoded_memWidth;
|
||||
wire _GEN =
|
||||
memIssue_0 ? _issue_io_out_0_decoded_memSigned : _issue_io_out_1_decoded_memSigned;
|
||||
wire _GEN_0 =
|
||||
memIssue_0 ? _issue_io_out_0_decoded_isStore : _issue_io_out_1_decoded_isStore;
|
||||
wire loadReq_isAmo =
|
||||
memIssue_0 ? _issue_io_out_0_decoded_isAmo : _issue_io_out_1_decoded_isAmo;
|
||||
wire [5:0] sq_io_enqRobIdx =
|
||||
memIssue_0 ? _issue_io_out_0_robIdx : _issue_io_out_1_robIdx;
|
||||
wire [63:0] _memAddr_T_1 =
|
||||
wire [63:0] _memAddr_T_2 =
|
||||
(memIssue_0 ? _prf_io_rdata_0 : _prf_io_rdata_2)
|
||||
+ (_GEN
|
||||
? (memIssue_0 ? _issue_io_out_0_decoded_immS : _issue_io_out_1_decoded_immS)
|
||||
: memIssue_0 ? _issue_io_out_0_decoded_immI : _issue_io_out_1_decoded_immI);
|
||||
+ (loadReq_isAmo
|
||||
? 64'h0
|
||||
: _GEN_0
|
||||
? (memIssue_0 ? _issue_io_out_0_decoded_immS : _issue_io_out_1_decoded_immS)
|
||||
: memIssue_0 ? _issue_io_out_0_decoded_immI : _issue_io_out_1_decoded_immI);
|
||||
wire _storeEnq_T = memIssue_0 | ~memIssue_0 & _issue_io_outValid_1 & isMem1;
|
||||
wire _GEN_0 = memIssue_0 ? issue_io_outReady_0 : issue_io_outReady_1;
|
||||
wire _GEN_1 = memIssue_0 ? issue_io_outReady_0 : issue_io_outReady_1;
|
||||
wire loadEnq =
|
||||
_storeEnq_T
|
||||
& (memIssue_0 ? _issue_io_out_0_decoded_isLoad : _issue_io_out_1_decoded_isLoad)
|
||||
& _GEN_0;
|
||||
wire storeEnq = _storeEnq_T & _GEN & _GEN_0;
|
||||
wire lsuLoadReq = loadEnq & ~_sq_io_forwardValid;
|
||||
& _GEN_1;
|
||||
wire storeEnq = _storeEnq_T & _GEN_0 & _GEN_1;
|
||||
wire sqForwardValid = _sq_io_forwardValid & ~loadReq_isAmo;
|
||||
wire lsuLoadReq = loadEnq & ~sqForwardValid;
|
||||
wire _commitCsr0_T = _commit_io_commitReady_0 & _rename_io_commitValid_0;
|
||||
wire commitStore0 = _commitCsr0_T & _rename_io_commitEntry_0_opClass == 4'h4;
|
||||
wire _commitCsr1_T = _commit_io_commitReady_1 & _rename_io_commitValid_1;
|
||||
wire commitStore0 = _commitCsr0_T & _rename_io_commitEntry_0_opClass == 4'h4;
|
||||
wire commitCsr0 = _commitCsr0_T & _rename_io_commitEntry_0_csrValid;
|
||||
wire _completeMispredict_0_T =
|
||||
_issue_io_out_0_decoded_isJal | _issue_io_out_0_decoded_isJalr;
|
||||
wire [63:0] _branchRedirect_T_1 = _issue_io_out_0_decoded_pc + 64'h4;
|
||||
wire [63:0] _jalrTarget_T = _prf_io_rdata_0 + _issue_io_out_0_decoded_immI;
|
||||
wire _completeMispredict_0_T_2 =
|
||||
wire _completeMispredict_0_T_3 =
|
||||
_issue_io_out_0_decoded_isBranch & _exec_0_io_branchTaken;
|
||||
wire isEcall = _issue_io_out_0_decoded_inst == 32'h73;
|
||||
wire isEbreak = _issue_io_out_0_decoded_inst == 32'h100073;
|
||||
wire isMret = _issue_io_out_0_decoded_inst == 32'h30200073;
|
||||
wire _completeCause_0_T = loadRespValid & _lsu_io_pageFault;
|
||||
wire _completeCause_0_T = loadRespValid & ~forwardPending & _lsu_io_pageFault;
|
||||
wire _completeMispredict_1_T =
|
||||
_issue_io_out_1_decoded_isJal | _issue_io_out_1_decoded_isJalr;
|
||||
wire [63:0] _branchRedirect_T_6 = _issue_io_out_1_decoded_pc + 64'h4;
|
||||
wire [63:0] _jalrTarget_T_3 = _prf_io_rdata_2 + _issue_io_out_1_decoded_immI;
|
||||
wire _completeMispredict_1_T_2 =
|
||||
wire _completeMispredict_1_T_3 =
|
||||
_issue_io_out_1_decoded_isBranch & _exec_1_io_branchTaken;
|
||||
wire isEcall_1 = _issue_io_out_1_decoded_inst == 32'h73;
|
||||
wire isEbreak_1 = _issue_io_out_1_decoded_inst == 32'h100073;
|
||||
wire isMret_1 = _issue_io_out_1_decoded_inst == 32'h30200073;
|
||||
always @(posedge clock) begin
|
||||
automatic logic _GEN_1;
|
||||
_GEN_1 = loadEnq & ~_sq_io_forwardValid;
|
||||
automatic logic [5:0] _GEN_2;
|
||||
automatic logic forwardLoad;
|
||||
automatic logic _GEN_3;
|
||||
automatic logic _GEN_4;
|
||||
_GEN_2 = memIssue_0 ? _issue_io_out_0_prd : _issue_io_out_1_prd;
|
||||
forwardLoad = loadEnq & sqForwardValid;
|
||||
_GEN_3 = loadEnq & ~sqForwardValid;
|
||||
_GEN_4 = forwardLoad | forwardPending;
|
||||
if (reset) begin
|
||||
wakeupReg_0_valid <= 1'h0;
|
||||
wakeupReg_0_phys <= 6'h0;
|
||||
wakeupReg_1_valid <= 1'h0;
|
||||
wakeupReg_1_phys <= 6'h0;
|
||||
loadPending <= 1'h0;
|
||||
forwardPending <= 1'h0;
|
||||
end
|
||||
else begin
|
||||
wakeupReg_0_valid <= _wb_0_io_wen;
|
||||
wakeupReg_0_phys <= _wb_0_io_waddr;
|
||||
wakeupReg_1_valid <= _wb_1_io_wen;
|
||||
wakeupReg_1_phys <= _wb_1_io_waddr;
|
||||
loadPending <= ~_commit_io_flush & (_GEN_1 | ~loadRespValid & loadPending);
|
||||
loadPending <=
|
||||
~_commit_io_flush
|
||||
& (_GEN_4 ? loadPending : _GEN_3 | ~loadRespValid & loadPending);
|
||||
forwardPending <= ~_commit_io_flush & forwardLoad;
|
||||
end
|
||||
if (_commit_io_flush | ~_GEN_1) begin
|
||||
if (_commit_io_flush | _GEN_4 | ~_GEN_3) begin
|
||||
end
|
||||
else begin
|
||||
loadPendingRob <= sq_io_enqRobIdx;
|
||||
loadPendingPhys <= memIssue_0 ? _issue_io_out_0_prd : _issue_io_out_1_prd;
|
||||
loadPendingPhys <= _GEN_2;
|
||||
loadPendingLq <= _lq_io_enqIdx;
|
||||
end
|
||||
if (_commit_io_flush | ~forwardLoad) begin
|
||||
end
|
||||
else begin
|
||||
forwardPendingRob <= sq_io_enqRobIdx;
|
||||
forwardPendingPhys <= _GEN_2;
|
||||
forwardPendingLq <= _lq_io_enqIdx;
|
||||
forwardPendingData <=
|
||||
sq_io_size == 3'h3
|
||||
? _sq_io_forwardData
|
||||
: sq_io_size == 3'h2
|
||||
? {_GEN ? {32{_sq_io_forwardData[31]}} : 32'h0, _sq_io_forwardData[31:0]}
|
||||
: sq_io_size == 3'h1
|
||||
? {_GEN ? {48{_sq_io_forwardData[15]}} : 48'h0,
|
||||
_sq_io_forwardData[15:0]}
|
||||
: sq_io_size == 3'h0
|
||||
? {_GEN ? {56{_sq_io_forwardData[7]}} : 56'h0,
|
||||
_sq_io_forwardData[7:0]}
|
||||
: _sq_io_forwardData;
|
||||
end
|
||||
end // always @(posedge)
|
||||
RenameStage rename (
|
||||
.clock (clock),
|
||||
@@ -381,6 +459,7 @@ module OoOBackend(
|
||||
.io_in_0_opClass (io_decode_0_opClass),
|
||||
.io_in_0_aluFn (io_decode_0_aluFn),
|
||||
.io_in_0_memWidth (io_decode_0_memWidth),
|
||||
.io_in_0_memSigned (io_decode_0_memSigned),
|
||||
.io_in_0_isLoad (io_decode_0_isLoad),
|
||||
.io_in_0_isStore (io_decode_0_isStore),
|
||||
.io_in_0_isBranch (io_decode_0_isBranch),
|
||||
@@ -391,6 +470,9 @@ module OoOBackend(
|
||||
.io_in_0_isOpImm (io_decode_0_isOpImm),
|
||||
.io_in_0_isWord (io_decode_0_isWord),
|
||||
.io_in_0_isSystem (io_decode_0_isSystem),
|
||||
.io_in_0_isFenceI (io_decode_0_isFenceI),
|
||||
.io_in_0_isAmo (io_decode_0_isAmo),
|
||||
.io_in_0_amoOp (io_decode_0_amoOp),
|
||||
.io_in_0_writesRd (io_decode_0_writesRd),
|
||||
.io_in_0_illegal (io_decode_0_illegal),
|
||||
.io_in_1_pc (io_decode_1_pc),
|
||||
@@ -407,6 +489,7 @@ module OoOBackend(
|
||||
.io_in_1_opClass (io_decode_1_opClass),
|
||||
.io_in_1_aluFn (io_decode_1_aluFn),
|
||||
.io_in_1_memWidth (io_decode_1_memWidth),
|
||||
.io_in_1_memSigned (io_decode_1_memSigned),
|
||||
.io_in_1_isLoad (io_decode_1_isLoad),
|
||||
.io_in_1_isStore (io_decode_1_isStore),
|
||||
.io_in_1_isBranch (io_decode_1_isBranch),
|
||||
@@ -417,6 +500,9 @@ module OoOBackend(
|
||||
.io_in_1_isOpImm (io_decode_1_isOpImm),
|
||||
.io_in_1_isWord (io_decode_1_isWord),
|
||||
.io_in_1_isSystem (io_decode_1_isSystem),
|
||||
.io_in_1_isFenceI (io_decode_1_isFenceI),
|
||||
.io_in_1_isAmo (io_decode_1_isAmo),
|
||||
.io_in_1_amoOp (io_decode_1_amoOp),
|
||||
.io_in_1_writesRd (io_decode_1_writesRd),
|
||||
.io_in_1_illegal (io_decode_1_illegal),
|
||||
.io_outValid_0 (_rename_io_outValid_0),
|
||||
@@ -433,6 +519,7 @@ module OoOBackend(
|
||||
.io_out_0_decoded_immJ (_rename_io_out_0_decoded_immJ),
|
||||
.io_out_0_decoded_aluFn (_rename_io_out_0_decoded_aluFn),
|
||||
.io_out_0_decoded_memWidth (_rename_io_out_0_decoded_memWidth),
|
||||
.io_out_0_decoded_memSigned (_rename_io_out_0_decoded_memSigned),
|
||||
.io_out_0_decoded_isLoad (_rename_io_out_0_decoded_isLoad),
|
||||
.io_out_0_decoded_isStore (_rename_io_out_0_decoded_isStore),
|
||||
.io_out_0_decoded_isBranch (_rename_io_out_0_decoded_isBranch),
|
||||
@@ -443,6 +530,9 @@ module OoOBackend(
|
||||
.io_out_0_decoded_isOpImm (_rename_io_out_0_decoded_isOpImm),
|
||||
.io_out_0_decoded_isWord (_rename_io_out_0_decoded_isWord),
|
||||
.io_out_0_decoded_isSystem (_rename_io_out_0_decoded_isSystem),
|
||||
.io_out_0_decoded_isFenceI (_rename_io_out_0_decoded_isFenceI),
|
||||
.io_out_0_decoded_isAmo (_rename_io_out_0_decoded_isAmo),
|
||||
.io_out_0_decoded_amoOp (_rename_io_out_0_decoded_amoOp),
|
||||
.io_out_0_decoded_writesRd (_rename_io_out_0_decoded_writesRd),
|
||||
.io_out_0_decoded_illegal (_rename_io_out_0_decoded_illegal),
|
||||
.io_out_0_prs1 (_rename_io_out_0_prs1),
|
||||
@@ -463,6 +553,7 @@ module OoOBackend(
|
||||
.io_out_1_decoded_immJ (_rename_io_out_1_decoded_immJ),
|
||||
.io_out_1_decoded_aluFn (_rename_io_out_1_decoded_aluFn),
|
||||
.io_out_1_decoded_memWidth (_rename_io_out_1_decoded_memWidth),
|
||||
.io_out_1_decoded_memSigned (_rename_io_out_1_decoded_memSigned),
|
||||
.io_out_1_decoded_isLoad (_rename_io_out_1_decoded_isLoad),
|
||||
.io_out_1_decoded_isStore (_rename_io_out_1_decoded_isStore),
|
||||
.io_out_1_decoded_isBranch (_rename_io_out_1_decoded_isBranch),
|
||||
@@ -473,6 +564,9 @@ module OoOBackend(
|
||||
.io_out_1_decoded_isOpImm (_rename_io_out_1_decoded_isOpImm),
|
||||
.io_out_1_decoded_isWord (_rename_io_out_1_decoded_isWord),
|
||||
.io_out_1_decoded_isSystem (_rename_io_out_1_decoded_isSystem),
|
||||
.io_out_1_decoded_isFenceI (_rename_io_out_1_decoded_isFenceI),
|
||||
.io_out_1_decoded_isAmo (_rename_io_out_1_decoded_isAmo),
|
||||
.io_out_1_decoded_amoOp (_rename_io_out_1_decoded_amoOp),
|
||||
.io_out_1_decoded_writesRd (_rename_io_out_1_decoded_writesRd),
|
||||
.io_out_1_decoded_illegal (_rename_io_out_1_decoded_illegal),
|
||||
.io_out_1_prs1 (_rename_io_out_1_prs1),
|
||||
@@ -490,7 +584,9 @@ module OoOBackend(
|
||||
(issueFire_0 & ~_issue_io_out_0_decoded_isLoad | loadRespValid),
|
||||
.io_completeValid_1 (issueFire_1 & ~_issue_io_out_1_decoded_isLoad),
|
||||
.io_completeIdx_0
|
||||
(loadRespValid ? loadPendingRob : _issue_io_out_0_robIdx),
|
||||
(loadRespValid
|
||||
? (forwardPending ? forwardPendingRob : loadPendingRob)
|
||||
: _issue_io_out_0_robIdx),
|
||||
.io_completeIdx_1 (_issue_io_out_1_robIdx),
|
||||
.io_completeException_0
|
||||
(issueFire_0
|
||||
@@ -518,9 +614,13 @@ module OoOBackend(
|
||||
.io_completeBadAddr_0 (_issue_io_out_0_decoded_pc),
|
||||
.io_completeBadAddr_1 (_issue_io_out_1_decoded_pc),
|
||||
.io_completeMispredict_0
|
||||
(issueFire_0 & (_completeMispredict_0_T | isMret | _completeMispredict_0_T_2)),
|
||||
(issueFire_0
|
||||
& (_completeMispredict_0_T | isMret | _issue_io_out_0_decoded_isFenceI
|
||||
| _completeMispredict_0_T_3)),
|
||||
.io_completeMispredict_1
|
||||
(issueFire_1 & (_completeMispredict_1_T | isMret_1 | _completeMispredict_1_T_2)),
|
||||
(issueFire_1
|
||||
& (_completeMispredict_1_T | isMret_1 | _issue_io_out_1_decoded_isFenceI
|
||||
| _completeMispredict_1_T_3)),
|
||||
.io_completeRedirectPc_0
|
||||
(isEcall | isEbreak
|
||||
? _csr_io_mtvec
|
||||
@@ -530,7 +630,7 @@ module OoOBackend(
|
||||
? _issue_io_out_0_decoded_pc + _issue_io_out_0_decoded_immJ
|
||||
: _issue_io_out_0_decoded_isJalr
|
||||
? {_jalrTarget_T[63:1], 1'h0}
|
||||
: _completeMispredict_0_T_2
|
||||
: _completeMispredict_0_T_3
|
||||
? _issue_io_out_0_decoded_pc + _issue_io_out_0_decoded_immB
|
||||
: _branchRedirect_T_1),
|
||||
.io_completeRedirectPc_1
|
||||
@@ -542,7 +642,7 @@ module OoOBackend(
|
||||
? _issue_io_out_1_decoded_pc + _issue_io_out_1_decoded_immJ
|
||||
: _issue_io_out_1_decoded_isJalr
|
||||
? {_jalrTarget_T_3[63:1], 1'h0}
|
||||
: _completeMispredict_1_T_2
|
||||
: _completeMispredict_1_T_3
|
||||
? _issue_io_out_1_decoded_pc + _issue_io_out_1_decoded_immB
|
||||
: _branchRedirect_T_6),
|
||||
.io_completeCsrValid_0
|
||||
@@ -579,6 +679,7 @@ module OoOBackend(
|
||||
.io_commitEntry_0_csrCmd (_rename_io_commitEntry_0_csrCmd),
|
||||
.io_commitEntry_0_csrRs1 (_rename_io_commitEntry_0_csrRs1),
|
||||
.io_commitEntry_0_csrZimm (_rename_io_commitEntry_0_csrZimm),
|
||||
.io_commitEntry_0_fenceI (_rename_io_commitEntry_0_fenceI),
|
||||
.io_commitEntry_1_robIdx (_rename_io_commitEntry_1_robIdx),
|
||||
.io_commitEntry_1_archDest (_rename_io_commitEntry_1_archDest),
|
||||
.io_commitEntry_1_writesDest (_rename_io_commitEntry_1_writesDest),
|
||||
@@ -595,6 +696,7 @@ module OoOBackend(
|
||||
.io_commitEntry_1_csrCmd (_rename_io_commitEntry_1_csrCmd),
|
||||
.io_commitEntry_1_csrRs1 (_rename_io_commitEntry_1_csrRs1),
|
||||
.io_commitEntry_1_csrZimm (_rename_io_commitEntry_1_csrZimm),
|
||||
.io_commitEntry_1_fenceI (_rename_io_commitEntry_1_fenceI),
|
||||
.io_commitMapValid_0 (_commit_io_commitMapValid_0),
|
||||
.io_commitMapValid_1 (_commit_io_commitMapValid_1),
|
||||
.io_commitArch_0 (_commit_io_commitArch_0),
|
||||
@@ -608,135 +710,151 @@ module OoOBackend(
|
||||
.io_flush (_commit_io_flush)
|
||||
);
|
||||
IssueStage issue (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_inValid_0 (_rename_io_outValid_0),
|
||||
.io_inValid_1 (_rename_io_outValid_1),
|
||||
.io_in_0_decoded_pc (_rename_io_out_0_decoded_pc),
|
||||
.io_in_0_decoded_inst (_rename_io_out_0_decoded_inst),
|
||||
.io_in_0_decoded_rs1 (_rename_io_out_0_decoded_rs1),
|
||||
.io_in_0_decoded_rs2 (_rename_io_out_0_decoded_rs2),
|
||||
.io_in_0_decoded_funct3 (_rename_io_out_0_decoded_funct3),
|
||||
.io_in_0_decoded_immI (_rename_io_out_0_decoded_immI),
|
||||
.io_in_0_decoded_immS (_rename_io_out_0_decoded_immS),
|
||||
.io_in_0_decoded_immB (_rename_io_out_0_decoded_immB),
|
||||
.io_in_0_decoded_immU (_rename_io_out_0_decoded_immU),
|
||||
.io_in_0_decoded_immJ (_rename_io_out_0_decoded_immJ),
|
||||
.io_in_0_decoded_aluFn (_rename_io_out_0_decoded_aluFn),
|
||||
.io_in_0_decoded_memWidth (_rename_io_out_0_decoded_memWidth),
|
||||
.io_in_0_decoded_isLoad (_rename_io_out_0_decoded_isLoad),
|
||||
.io_in_0_decoded_isStore (_rename_io_out_0_decoded_isStore),
|
||||
.io_in_0_decoded_isBranch (_rename_io_out_0_decoded_isBranch),
|
||||
.io_in_0_decoded_isJal (_rename_io_out_0_decoded_isJal),
|
||||
.io_in_0_decoded_isJalr (_rename_io_out_0_decoded_isJalr),
|
||||
.io_in_0_decoded_isLui (_rename_io_out_0_decoded_isLui),
|
||||
.io_in_0_decoded_isAuipc (_rename_io_out_0_decoded_isAuipc),
|
||||
.io_in_0_decoded_isOpImm (_rename_io_out_0_decoded_isOpImm),
|
||||
.io_in_0_decoded_isWord (_rename_io_out_0_decoded_isWord),
|
||||
.io_in_0_decoded_isSystem (_rename_io_out_0_decoded_isSystem),
|
||||
.io_in_0_decoded_writesRd (_rename_io_out_0_decoded_writesRd),
|
||||
.io_in_0_decoded_illegal (_rename_io_out_0_decoded_illegal),
|
||||
.io_in_0_prs1 (_rename_io_out_0_prs1),
|
||||
.io_in_0_prs2 (_rename_io_out_0_prs2),
|
||||
.io_in_0_src1Ready (_rename_io_out_0_src1Ready),
|
||||
.io_in_0_src2Ready (_rename_io_out_0_src2Ready),
|
||||
.io_in_0_prd (_rename_io_out_0_prd),
|
||||
.io_in_0_robIdx (_rename_io_out_0_robIdx),
|
||||
.io_in_1_decoded_pc (_rename_io_out_1_decoded_pc),
|
||||
.io_in_1_decoded_inst (_rename_io_out_1_decoded_inst),
|
||||
.io_in_1_decoded_rs1 (_rename_io_out_1_decoded_rs1),
|
||||
.io_in_1_decoded_rs2 (_rename_io_out_1_decoded_rs2),
|
||||
.io_in_1_decoded_funct3 (_rename_io_out_1_decoded_funct3),
|
||||
.io_in_1_decoded_immI (_rename_io_out_1_decoded_immI),
|
||||
.io_in_1_decoded_immS (_rename_io_out_1_decoded_immS),
|
||||
.io_in_1_decoded_immB (_rename_io_out_1_decoded_immB),
|
||||
.io_in_1_decoded_immU (_rename_io_out_1_decoded_immU),
|
||||
.io_in_1_decoded_immJ (_rename_io_out_1_decoded_immJ),
|
||||
.io_in_1_decoded_aluFn (_rename_io_out_1_decoded_aluFn),
|
||||
.io_in_1_decoded_memWidth (_rename_io_out_1_decoded_memWidth),
|
||||
.io_in_1_decoded_isLoad (_rename_io_out_1_decoded_isLoad),
|
||||
.io_in_1_decoded_isStore (_rename_io_out_1_decoded_isStore),
|
||||
.io_in_1_decoded_isBranch (_rename_io_out_1_decoded_isBranch),
|
||||
.io_in_1_decoded_isJal (_rename_io_out_1_decoded_isJal),
|
||||
.io_in_1_decoded_isJalr (_rename_io_out_1_decoded_isJalr),
|
||||
.io_in_1_decoded_isLui (_rename_io_out_1_decoded_isLui),
|
||||
.io_in_1_decoded_isAuipc (_rename_io_out_1_decoded_isAuipc),
|
||||
.io_in_1_decoded_isOpImm (_rename_io_out_1_decoded_isOpImm),
|
||||
.io_in_1_decoded_isWord (_rename_io_out_1_decoded_isWord),
|
||||
.io_in_1_decoded_isSystem (_rename_io_out_1_decoded_isSystem),
|
||||
.io_in_1_decoded_writesRd (_rename_io_out_1_decoded_writesRd),
|
||||
.io_in_1_decoded_illegal (_rename_io_out_1_decoded_illegal),
|
||||
.io_in_1_prs1 (_rename_io_out_1_prs1),
|
||||
.io_in_1_prs2 (_rename_io_out_1_prs2),
|
||||
.io_in_1_src1Ready (_rename_io_out_1_src1Ready),
|
||||
.io_in_1_src2Ready (_rename_io_out_1_src2Ready),
|
||||
.io_in_1_prd (_rename_io_out_1_prd),
|
||||
.io_in_1_robIdx (_rename_io_out_1_robIdx),
|
||||
.io_inReady_0 (_issue_io_inReady_0),
|
||||
.io_inReady_1 (_issue_io_inReady_1),
|
||||
.io_wakeup_0_valid (wakeupReg_0_valid),
|
||||
.io_wakeup_0_phys (wakeupReg_0_phys),
|
||||
.io_wakeup_1_valid (wakeupReg_1_valid),
|
||||
.io_wakeup_1_phys (wakeupReg_1_phys),
|
||||
.io_outValid_0 (_issue_io_outValid_0),
|
||||
.io_outValid_1 (_issue_io_outValid_1),
|
||||
.io_out_0_decoded_pc (_issue_io_out_0_decoded_pc),
|
||||
.io_out_0_decoded_inst (_issue_io_out_0_decoded_inst),
|
||||
.io_out_0_decoded_rs1 (_issue_io_out_0_decoded_rs1),
|
||||
.io_out_0_decoded_funct3 (_issue_io_out_0_decoded_funct3),
|
||||
.io_out_0_decoded_immI (_issue_io_out_0_decoded_immI),
|
||||
.io_out_0_decoded_immS (_issue_io_out_0_decoded_immS),
|
||||
.io_out_0_decoded_immB (_issue_io_out_0_decoded_immB),
|
||||
.io_out_0_decoded_immU (_issue_io_out_0_decoded_immU),
|
||||
.io_out_0_decoded_immJ (_issue_io_out_0_decoded_immJ),
|
||||
.io_out_0_decoded_aluFn (_issue_io_out_0_decoded_aluFn),
|
||||
.io_out_0_decoded_memWidth (_issue_io_out_0_decoded_memWidth),
|
||||
.io_out_0_decoded_isLoad (_issue_io_out_0_decoded_isLoad),
|
||||
.io_out_0_decoded_isStore (_issue_io_out_0_decoded_isStore),
|
||||
.io_out_0_decoded_isBranch (_issue_io_out_0_decoded_isBranch),
|
||||
.io_out_0_decoded_isJal (_issue_io_out_0_decoded_isJal),
|
||||
.io_out_0_decoded_isJalr (_issue_io_out_0_decoded_isJalr),
|
||||
.io_out_0_decoded_isLui (_issue_io_out_0_decoded_isLui),
|
||||
.io_out_0_decoded_isAuipc (_issue_io_out_0_decoded_isAuipc),
|
||||
.io_out_0_decoded_isOpImm (_issue_io_out_0_decoded_isOpImm),
|
||||
.io_out_0_decoded_isWord (_issue_io_out_0_decoded_isWord),
|
||||
.io_out_0_decoded_isSystem (_issue_io_out_0_decoded_isSystem),
|
||||
.io_out_0_decoded_writesRd (_issue_io_out_0_decoded_writesRd),
|
||||
.io_out_0_decoded_illegal (_issue_io_out_0_decoded_illegal),
|
||||
.io_out_0_prs1 (_issue_io_out_0_prs1),
|
||||
.io_out_0_prs2 (_issue_io_out_0_prs2),
|
||||
.io_out_0_prd (_issue_io_out_0_prd),
|
||||
.io_out_0_robIdx (_issue_io_out_0_robIdx),
|
||||
.io_out_1_decoded_pc (_issue_io_out_1_decoded_pc),
|
||||
.io_out_1_decoded_inst (_issue_io_out_1_decoded_inst),
|
||||
.io_out_1_decoded_rs1 (_issue_io_out_1_decoded_rs1),
|
||||
.io_out_1_decoded_funct3 (_issue_io_out_1_decoded_funct3),
|
||||
.io_out_1_decoded_immI (_issue_io_out_1_decoded_immI),
|
||||
.io_out_1_decoded_immS (_issue_io_out_1_decoded_immS),
|
||||
.io_out_1_decoded_immB (_issue_io_out_1_decoded_immB),
|
||||
.io_out_1_decoded_immU (_issue_io_out_1_decoded_immU),
|
||||
.io_out_1_decoded_immJ (_issue_io_out_1_decoded_immJ),
|
||||
.io_out_1_decoded_aluFn (_issue_io_out_1_decoded_aluFn),
|
||||
.io_out_1_decoded_memWidth (_issue_io_out_1_decoded_memWidth),
|
||||
.io_out_1_decoded_isLoad (_issue_io_out_1_decoded_isLoad),
|
||||
.io_out_1_decoded_isStore (_issue_io_out_1_decoded_isStore),
|
||||
.io_out_1_decoded_isBranch (_issue_io_out_1_decoded_isBranch),
|
||||
.io_out_1_decoded_isJal (_issue_io_out_1_decoded_isJal),
|
||||
.io_out_1_decoded_isJalr (_issue_io_out_1_decoded_isJalr),
|
||||
.io_out_1_decoded_isLui (_issue_io_out_1_decoded_isLui),
|
||||
.io_out_1_decoded_isAuipc (_issue_io_out_1_decoded_isAuipc),
|
||||
.io_out_1_decoded_isOpImm (_issue_io_out_1_decoded_isOpImm),
|
||||
.io_out_1_decoded_isWord (_issue_io_out_1_decoded_isWord),
|
||||
.io_out_1_decoded_isSystem (_issue_io_out_1_decoded_isSystem),
|
||||
.io_out_1_decoded_writesRd (_issue_io_out_1_decoded_writesRd),
|
||||
.io_out_1_decoded_illegal (_issue_io_out_1_decoded_illegal),
|
||||
.io_out_1_prs1 (_issue_io_out_1_prs1),
|
||||
.io_out_1_prs2 (_issue_io_out_1_prs2),
|
||||
.io_out_1_prd (_issue_io_out_1_prd),
|
||||
.io_out_1_robIdx (_issue_io_out_1_robIdx),
|
||||
.io_outReady_0 (issue_io_outReady_0),
|
||||
.io_outReady_1 (issue_io_outReady_1),
|
||||
.io_flush (_commit_io_flush)
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_inValid_0 (_rename_io_outValid_0),
|
||||
.io_inValid_1 (_rename_io_outValid_1),
|
||||
.io_in_0_decoded_pc (_rename_io_out_0_decoded_pc),
|
||||
.io_in_0_decoded_inst (_rename_io_out_0_decoded_inst),
|
||||
.io_in_0_decoded_rs1 (_rename_io_out_0_decoded_rs1),
|
||||
.io_in_0_decoded_rs2 (_rename_io_out_0_decoded_rs2),
|
||||
.io_in_0_decoded_funct3 (_rename_io_out_0_decoded_funct3),
|
||||
.io_in_0_decoded_immI (_rename_io_out_0_decoded_immI),
|
||||
.io_in_0_decoded_immS (_rename_io_out_0_decoded_immS),
|
||||
.io_in_0_decoded_immB (_rename_io_out_0_decoded_immB),
|
||||
.io_in_0_decoded_immU (_rename_io_out_0_decoded_immU),
|
||||
.io_in_0_decoded_immJ (_rename_io_out_0_decoded_immJ),
|
||||
.io_in_0_decoded_aluFn (_rename_io_out_0_decoded_aluFn),
|
||||
.io_in_0_decoded_memWidth (_rename_io_out_0_decoded_memWidth),
|
||||
.io_in_0_decoded_memSigned (_rename_io_out_0_decoded_memSigned),
|
||||
.io_in_0_decoded_isLoad (_rename_io_out_0_decoded_isLoad),
|
||||
.io_in_0_decoded_isStore (_rename_io_out_0_decoded_isStore),
|
||||
.io_in_0_decoded_isBranch (_rename_io_out_0_decoded_isBranch),
|
||||
.io_in_0_decoded_isJal (_rename_io_out_0_decoded_isJal),
|
||||
.io_in_0_decoded_isJalr (_rename_io_out_0_decoded_isJalr),
|
||||
.io_in_0_decoded_isLui (_rename_io_out_0_decoded_isLui),
|
||||
.io_in_0_decoded_isAuipc (_rename_io_out_0_decoded_isAuipc),
|
||||
.io_in_0_decoded_isOpImm (_rename_io_out_0_decoded_isOpImm),
|
||||
.io_in_0_decoded_isWord (_rename_io_out_0_decoded_isWord),
|
||||
.io_in_0_decoded_isSystem (_rename_io_out_0_decoded_isSystem),
|
||||
.io_in_0_decoded_isFenceI (_rename_io_out_0_decoded_isFenceI),
|
||||
.io_in_0_decoded_isAmo (_rename_io_out_0_decoded_isAmo),
|
||||
.io_in_0_decoded_amoOp (_rename_io_out_0_decoded_amoOp),
|
||||
.io_in_0_decoded_writesRd (_rename_io_out_0_decoded_writesRd),
|
||||
.io_in_0_decoded_illegal (_rename_io_out_0_decoded_illegal),
|
||||
.io_in_0_prs1 (_rename_io_out_0_prs1),
|
||||
.io_in_0_prs2 (_rename_io_out_0_prs2),
|
||||
.io_in_0_src1Ready (_rename_io_out_0_src1Ready),
|
||||
.io_in_0_src2Ready (_rename_io_out_0_src2Ready),
|
||||
.io_in_0_prd (_rename_io_out_0_prd),
|
||||
.io_in_0_robIdx (_rename_io_out_0_robIdx),
|
||||
.io_in_1_decoded_pc (_rename_io_out_1_decoded_pc),
|
||||
.io_in_1_decoded_inst (_rename_io_out_1_decoded_inst),
|
||||
.io_in_1_decoded_rs1 (_rename_io_out_1_decoded_rs1),
|
||||
.io_in_1_decoded_rs2 (_rename_io_out_1_decoded_rs2),
|
||||
.io_in_1_decoded_funct3 (_rename_io_out_1_decoded_funct3),
|
||||
.io_in_1_decoded_immI (_rename_io_out_1_decoded_immI),
|
||||
.io_in_1_decoded_immS (_rename_io_out_1_decoded_immS),
|
||||
.io_in_1_decoded_immB (_rename_io_out_1_decoded_immB),
|
||||
.io_in_1_decoded_immU (_rename_io_out_1_decoded_immU),
|
||||
.io_in_1_decoded_immJ (_rename_io_out_1_decoded_immJ),
|
||||
.io_in_1_decoded_aluFn (_rename_io_out_1_decoded_aluFn),
|
||||
.io_in_1_decoded_memWidth (_rename_io_out_1_decoded_memWidth),
|
||||
.io_in_1_decoded_memSigned (_rename_io_out_1_decoded_memSigned),
|
||||
.io_in_1_decoded_isLoad (_rename_io_out_1_decoded_isLoad),
|
||||
.io_in_1_decoded_isStore (_rename_io_out_1_decoded_isStore),
|
||||
.io_in_1_decoded_isBranch (_rename_io_out_1_decoded_isBranch),
|
||||
.io_in_1_decoded_isJal (_rename_io_out_1_decoded_isJal),
|
||||
.io_in_1_decoded_isJalr (_rename_io_out_1_decoded_isJalr),
|
||||
.io_in_1_decoded_isLui (_rename_io_out_1_decoded_isLui),
|
||||
.io_in_1_decoded_isAuipc (_rename_io_out_1_decoded_isAuipc),
|
||||
.io_in_1_decoded_isOpImm (_rename_io_out_1_decoded_isOpImm),
|
||||
.io_in_1_decoded_isWord (_rename_io_out_1_decoded_isWord),
|
||||
.io_in_1_decoded_isSystem (_rename_io_out_1_decoded_isSystem),
|
||||
.io_in_1_decoded_isFenceI (_rename_io_out_1_decoded_isFenceI),
|
||||
.io_in_1_decoded_isAmo (_rename_io_out_1_decoded_isAmo),
|
||||
.io_in_1_decoded_amoOp (_rename_io_out_1_decoded_amoOp),
|
||||
.io_in_1_decoded_writesRd (_rename_io_out_1_decoded_writesRd),
|
||||
.io_in_1_decoded_illegal (_rename_io_out_1_decoded_illegal),
|
||||
.io_in_1_prs1 (_rename_io_out_1_prs1),
|
||||
.io_in_1_prs2 (_rename_io_out_1_prs2),
|
||||
.io_in_1_src1Ready (_rename_io_out_1_src1Ready),
|
||||
.io_in_1_src2Ready (_rename_io_out_1_src2Ready),
|
||||
.io_in_1_prd (_rename_io_out_1_prd),
|
||||
.io_in_1_robIdx (_rename_io_out_1_robIdx),
|
||||
.io_inReady_0 (_issue_io_inReady_0),
|
||||
.io_inReady_1 (_issue_io_inReady_1),
|
||||
.io_wakeup_0_valid (wakeupReg_0_valid),
|
||||
.io_wakeup_0_phys (wakeupReg_0_phys),
|
||||
.io_wakeup_1_valid (wakeupReg_1_valid),
|
||||
.io_wakeup_1_phys (wakeupReg_1_phys),
|
||||
.io_outValid_0 (_issue_io_outValid_0),
|
||||
.io_outValid_1 (_issue_io_outValid_1),
|
||||
.io_out_0_decoded_pc (_issue_io_out_0_decoded_pc),
|
||||
.io_out_0_decoded_inst (_issue_io_out_0_decoded_inst),
|
||||
.io_out_0_decoded_rs1 (_issue_io_out_0_decoded_rs1),
|
||||
.io_out_0_decoded_funct3 (_issue_io_out_0_decoded_funct3),
|
||||
.io_out_0_decoded_immI (_issue_io_out_0_decoded_immI),
|
||||
.io_out_0_decoded_immS (_issue_io_out_0_decoded_immS),
|
||||
.io_out_0_decoded_immB (_issue_io_out_0_decoded_immB),
|
||||
.io_out_0_decoded_immU (_issue_io_out_0_decoded_immU),
|
||||
.io_out_0_decoded_immJ (_issue_io_out_0_decoded_immJ),
|
||||
.io_out_0_decoded_aluFn (_issue_io_out_0_decoded_aluFn),
|
||||
.io_out_0_decoded_memWidth (_issue_io_out_0_decoded_memWidth),
|
||||
.io_out_0_decoded_memSigned (_issue_io_out_0_decoded_memSigned),
|
||||
.io_out_0_decoded_isLoad (_issue_io_out_0_decoded_isLoad),
|
||||
.io_out_0_decoded_isStore (_issue_io_out_0_decoded_isStore),
|
||||
.io_out_0_decoded_isBranch (_issue_io_out_0_decoded_isBranch),
|
||||
.io_out_0_decoded_isJal (_issue_io_out_0_decoded_isJal),
|
||||
.io_out_0_decoded_isJalr (_issue_io_out_0_decoded_isJalr),
|
||||
.io_out_0_decoded_isLui (_issue_io_out_0_decoded_isLui),
|
||||
.io_out_0_decoded_isAuipc (_issue_io_out_0_decoded_isAuipc),
|
||||
.io_out_0_decoded_isOpImm (_issue_io_out_0_decoded_isOpImm),
|
||||
.io_out_0_decoded_isWord (_issue_io_out_0_decoded_isWord),
|
||||
.io_out_0_decoded_isSystem (_issue_io_out_0_decoded_isSystem),
|
||||
.io_out_0_decoded_isFenceI (_issue_io_out_0_decoded_isFenceI),
|
||||
.io_out_0_decoded_isAmo (_issue_io_out_0_decoded_isAmo),
|
||||
.io_out_0_decoded_amoOp (_issue_io_out_0_decoded_amoOp),
|
||||
.io_out_0_decoded_writesRd (_issue_io_out_0_decoded_writesRd),
|
||||
.io_out_0_decoded_illegal (_issue_io_out_0_decoded_illegal),
|
||||
.io_out_0_prs1 (_issue_io_out_0_prs1),
|
||||
.io_out_0_prs2 (_issue_io_out_0_prs2),
|
||||
.io_out_0_prd (_issue_io_out_0_prd),
|
||||
.io_out_0_robIdx (_issue_io_out_0_robIdx),
|
||||
.io_out_1_decoded_pc (_issue_io_out_1_decoded_pc),
|
||||
.io_out_1_decoded_inst (_issue_io_out_1_decoded_inst),
|
||||
.io_out_1_decoded_rs1 (_issue_io_out_1_decoded_rs1),
|
||||
.io_out_1_decoded_funct3 (_issue_io_out_1_decoded_funct3),
|
||||
.io_out_1_decoded_immI (_issue_io_out_1_decoded_immI),
|
||||
.io_out_1_decoded_immS (_issue_io_out_1_decoded_immS),
|
||||
.io_out_1_decoded_immB (_issue_io_out_1_decoded_immB),
|
||||
.io_out_1_decoded_immU (_issue_io_out_1_decoded_immU),
|
||||
.io_out_1_decoded_immJ (_issue_io_out_1_decoded_immJ),
|
||||
.io_out_1_decoded_aluFn (_issue_io_out_1_decoded_aluFn),
|
||||
.io_out_1_decoded_memWidth (_issue_io_out_1_decoded_memWidth),
|
||||
.io_out_1_decoded_memSigned (_issue_io_out_1_decoded_memSigned),
|
||||
.io_out_1_decoded_isLoad (_issue_io_out_1_decoded_isLoad),
|
||||
.io_out_1_decoded_isStore (_issue_io_out_1_decoded_isStore),
|
||||
.io_out_1_decoded_isBranch (_issue_io_out_1_decoded_isBranch),
|
||||
.io_out_1_decoded_isJal (_issue_io_out_1_decoded_isJal),
|
||||
.io_out_1_decoded_isJalr (_issue_io_out_1_decoded_isJalr),
|
||||
.io_out_1_decoded_isLui (_issue_io_out_1_decoded_isLui),
|
||||
.io_out_1_decoded_isAuipc (_issue_io_out_1_decoded_isAuipc),
|
||||
.io_out_1_decoded_isOpImm (_issue_io_out_1_decoded_isOpImm),
|
||||
.io_out_1_decoded_isWord (_issue_io_out_1_decoded_isWord),
|
||||
.io_out_1_decoded_isSystem (_issue_io_out_1_decoded_isSystem),
|
||||
.io_out_1_decoded_isFenceI (_issue_io_out_1_decoded_isFenceI),
|
||||
.io_out_1_decoded_isAmo (_issue_io_out_1_decoded_isAmo),
|
||||
.io_out_1_decoded_amoOp (_issue_io_out_1_decoded_amoOp),
|
||||
.io_out_1_decoded_writesRd (_issue_io_out_1_decoded_writesRd),
|
||||
.io_out_1_decoded_illegal (_issue_io_out_1_decoded_illegal),
|
||||
.io_out_1_prs1 (_issue_io_out_1_prs1),
|
||||
.io_out_1_prs2 (_issue_io_out_1_prs2),
|
||||
.io_out_1_prd (_issue_io_out_1_prd),
|
||||
.io_out_1_robIdx (_issue_io_out_1_robIdx),
|
||||
.io_outReady_0 (issue_io_outReady_0),
|
||||
.io_outReady_1 (issue_io_outReady_1),
|
||||
.io_flush (_commit_io_flush)
|
||||
);
|
||||
PhysicalRegFile prf (
|
||||
.clock (clock),
|
||||
@@ -790,10 +908,13 @@ module OoOBackend(
|
||||
.io_valid
|
||||
(_exec_0_io_outValid & _issue_io_out_0_decoded_writesRd
|
||||
& ~_issue_io_out_0_decoded_isLoad | loadRespValid),
|
||||
.io_physDest (loadRespValid ? loadPendingPhys : _issue_io_out_0_prd),
|
||||
.io_physDest
|
||||
(loadRespValid
|
||||
? (forwardPending ? forwardPendingPhys : loadPendingPhys)
|
||||
: _issue_io_out_0_prd),
|
||||
.io_data
|
||||
(loadRespValid
|
||||
? _lsu_io_respData
|
||||
? (forwardPending ? forwardPendingData : _lsu_io_respData)
|
||||
: _issue_io_out_0_decoded_isLui
|
||||
? _issue_io_out_0_decoded_immU
|
||||
: _issue_io_out_0_decoded_isAuipc
|
||||
@@ -841,6 +962,7 @@ module OoOBackend(
|
||||
.io_robEntry_0_branchMispredict (_rename_io_commitEntry_0_branchMispredict),
|
||||
.io_robEntry_0_redirectPc (_rename_io_commitEntry_0_redirectPc),
|
||||
.io_robEntry_0_csrValid (_rename_io_commitEntry_0_csrValid),
|
||||
.io_robEntry_0_fenceI (_rename_io_commitEntry_0_fenceI),
|
||||
.io_robEntry_1_archDest (_rename_io_commitEntry_1_archDest),
|
||||
.io_robEntry_1_writesDest (_rename_io_commitEntry_1_writesDest),
|
||||
.io_robEntry_1_dest (_rename_io_commitEntry_1_dest),
|
||||
@@ -851,6 +973,7 @@ module OoOBackend(
|
||||
.io_robEntry_1_branchMispredict (_rename_io_commitEntry_1_branchMispredict),
|
||||
.io_robEntry_1_redirectPc (_rename_io_commitEntry_1_redirectPc),
|
||||
.io_robEntry_1_csrValid (_rename_io_commitEntry_1_csrValid),
|
||||
.io_robEntry_1_fenceI (_rename_io_commitEntry_1_fenceI),
|
||||
.io_commitReady_0 (_commit_io_commitReady_0),
|
||||
.io_commitReady_1 (_commit_io_commitReady_1),
|
||||
.io_freeOldPhys_0 (_commit_io_freeOldPhys_0),
|
||||
@@ -867,7 +990,8 @@ module OoOBackend(
|
||||
.io_redirectPc (_commit_io_redirectPc),
|
||||
.io_exception (_commit_io_exception),
|
||||
.io_exceptionCause (_commit_io_exceptionCause),
|
||||
.io_badAddr (_commit_io_badAddr)
|
||||
.io_badAddr (_commit_io_badAddr),
|
||||
.io_fenceI (io_invalidateICache)
|
||||
);
|
||||
LoadQueue lq (
|
||||
.clock (clock),
|
||||
@@ -877,53 +1001,65 @@ module OoOBackend(
|
||||
.io_enqIdx (_lq_io_enqIdx),
|
||||
.io_addrValid (loadEnq),
|
||||
.io_addrIdx (_lq_io_enqIdx),
|
||||
.io_addr (_memAddr_T_1),
|
||||
.io_addr (_memAddr_T_2),
|
||||
.io_size (sq_io_size),
|
||||
.io_complete (loadRespValid),
|
||||
.io_completeIdx (loadPendingLq),
|
||||
.io_completeIdx (forwardPending ? forwardPendingLq : loadPendingLq),
|
||||
.io_commitValid_0 (_commitCsr0_T & _rename_io_commitEntry_0_opClass == 4'h3),
|
||||
.io_commitValid_1 (_commitCsr1_T & _rename_io_commitEntry_1_opClass == 4'h3),
|
||||
.io_commitRobIdx_0 (_rename_io_commitEntry_0_robIdx),
|
||||
.io_commitRobIdx_1 (_rename_io_commitEntry_1_robIdx),
|
||||
.io_storeAddrValid (storeEnq),
|
||||
.io_storeRobIdx (sq_io_enqRobIdx),
|
||||
.io_storeAddr (_memAddr_T_1),
|
||||
.io_storeAddr (_memAddr_T_2),
|
||||
.io_storeSize (sq_io_size),
|
||||
.io_violation (_lq_io_violation),
|
||||
.io_flush (_commit_io_flush)
|
||||
);
|
||||
StoreQueue sq (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_enqValid (storeEnq),
|
||||
.io_enqRobIdx (sq_io_enqRobIdx),
|
||||
.io_enqIdx (_sq_io_enqIdx),
|
||||
.io_writeAddr (storeEnq),
|
||||
.io_writeData (storeEnq),
|
||||
.io_writeIdx (_sq_io_enqIdx),
|
||||
.io_addr (_memAddr_T_1),
|
||||
.io_data (memIssue_0 ? _prf_io_rdata_1 : _prf_io_rdata_3),
|
||||
.io_size (sq_io_size),
|
||||
.io_loadAddr (_memAddr_T_1),
|
||||
.io_loadRobIdx (sq_io_enqRobIdx),
|
||||
.io_forwardValid (_sq_io_forwardValid),
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_enqValid (storeEnq),
|
||||
.io_enqRobIdx (sq_io_enqRobIdx),
|
||||
.io_enqIdx (_sq_io_enqIdx),
|
||||
.io_writeAddr (storeEnq),
|
||||
.io_writeData (storeEnq),
|
||||
.io_writeIdx (_sq_io_enqIdx),
|
||||
.io_addr (_memAddr_T_2),
|
||||
.io_data (memSrc2),
|
||||
.io_size (sq_io_size),
|
||||
.io_loadAddr (_memAddr_T_2),
|
||||
.io_loadSize (sq_io_size),
|
||||
.io_loadRobIdx (sq_io_enqRobIdx),
|
||||
.io_forwardValid (_sq_io_forwardValid),
|
||||
.io_forwardData (_sq_io_forwardData),
|
||||
.io_forwardBlock (_sq_io_forwardBlock),
|
||||
.io_olderStoreValid (_sq_io_olderStoreValid),
|
||||
.io_commitValid
|
||||
(commitStore0 | _commitCsr1_T & _rename_io_commitEntry_1_opClass == 4'h4),
|
||||
.io_commitRobIdx
|
||||
(commitStore0 ? _rename_io_commitEntry_0_robIdx : _rename_io_commitEntry_1_robIdx),
|
||||
.io_drainValid (_sq_io_drainValid),
|
||||
.io_drain_addr (_sq_io_drain_addr),
|
||||
.io_drain_data (_sq_io_drain_data),
|
||||
.io_drain_size (_sq_io_drain_size),
|
||||
.io_drainReady (~lsuLoadReq & _lsu_io_reqReady),
|
||||
.io_flush (_commit_io_flush)
|
||||
.io_drainValid (_sq_io_drainValid),
|
||||
.io_drain_addr (_sq_io_drain_addr),
|
||||
.io_drain_data (_sq_io_drain_data),
|
||||
.io_drain_size (_sq_io_drain_size),
|
||||
.io_drainReady (~lsuLoadReq & _lsu_io_reqReady),
|
||||
.io_flush (_commit_io_flush)
|
||||
);
|
||||
LSU lsu (
|
||||
.clock (clock),
|
||||
.reset (reset),
|
||||
.io_reqValid (lsuLoadReq | _sq_io_drainValid),
|
||||
.io_req_addr
|
||||
(lsuLoadReq ? _memAddr_T_1 : _sq_io_drainValid ? _sq_io_drain_addr : 64'h0),
|
||||
.io_req_data (lsuLoadReq | ~_sq_io_drainValid ? 64'h0 : _sq_io_drain_data),
|
||||
.io_req_isStore (~lsuLoadReq & _sq_io_drainValid),
|
||||
.io_req_size
|
||||
(lsuLoadReq ? sq_io_size : _sq_io_drainValid ? _sq_io_drain_size : 3'h0),
|
||||
.io_req_addr (lsuLoadReq ? _memAddr_T_2 : _sq_io_drain_addr),
|
||||
.io_req_data (lsuLoadReq ? memSrc2 : _sq_io_drain_data),
|
||||
.io_req_isStore (~lsuLoadReq),
|
||||
.io_req_isSigned (lsuLoadReq & (_GEN | loadReq_isAmo)),
|
||||
.io_req_isAmo (lsuLoadReq & loadReq_isAmo),
|
||||
.io_req_amoOp
|
||||
(lsuLoadReq
|
||||
? (memIssue_0 ? _issue_io_out_0_decoded_amoOp : _issue_io_out_1_decoded_amoOp)
|
||||
: 5'h0),
|
||||
.io_req_size (lsuLoadReq ? sq_io_size : _sq_io_drain_size),
|
||||
.io_reqReady (_lsu_io_reqReady),
|
||||
.io_satp (_csr_io_satp),
|
||||
.io_dmemReqValid (io_dmemReqValid),
|
||||
|
||||
Reference in New Issue
Block a user