fix: pass remaining riscv isa tests

2026-06-27 07:07:07 +00:00
parent a2e0126199
commit a32db39c80
38 changed files with 81187 additions and 19321 deletions
--- a/generated-ooo/Frontend.sv
+++ b/generated-ooo/Frontend.sv
@@ -4,6 +4,7 @@ module Frontend(
                reset,
                io_redirectValid,
  input  [63:0] io_redirectPc,
+  input         io_invalidateICache,
  output        io_imemReqValid,
  output [63:0] io_imemReqAddr,
  input         io_imemRespValid,
@@ -41,6 +42,7 @@ module Frontend(
    .io_reqAddr          (pc),
    .io_reqPc            (pc),
    .io_flush            (io_redirectValid),
+    .io_invalidate       (io_invalidateICache),
    .io_respReady        (io_outReady),
    .io_memReqValid      (io_imemReqValid),
    .io_memReqAddr       (io_imemReqAddr),