fix: pass remaining riscv isa tests

generated-ooo/CommitStage.sv

@@ -13,6 +13,7 @@ module CommitStage(
   input         io_robEntry_0_branchMispredict,
   input  [63:0] io_robEntry_0_redirectPc,
   input         io_robEntry_0_csrValid,
+                io_robEntry_0_fenceI,
   input  [4:0]  io_robEntry_1_archDest,
   input         io_robEntry_1_writesDest,
   input  [5:0]  io_robEntry_1_dest,
@@ -23,6 +24,7 @@ module CommitStage(
   input         io_robEntry_1_branchMispredict,
   input  [63:0] io_robEntry_1_redirectPc,
   input         io_robEntry_1_csrValid,
+                io_robEntry_1_fenceI,
   output        io_commitReady_0,
                 io_commitReady_1,
                 io_freeOldPhys_0,
@@ -39,7 +41,8 @@ module CommitStage(
   output [63:0] io_redirectPc,
   output        io_exception,
   output [63:0] io_exceptionCause,
-                io_badAddr
+                io_badAddr,
+  output        io_fenceI
 );
 
   wire firstTrap =
@@ -79,5 +82,7 @@ module CommitStage(
     firstTrap
       ? io_robEntry_0_badAddr
       : secondTrapSelected ? io_robEntry_1_badAddr : 64'h0;
+  assign io_fenceI =
+    io_robValid_0 & io_robEntry_0_fenceI | io_commitReady_1_0 & io_robEntry_1_fenceI;
 endmodule