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fix: pass remaining riscv isa tests

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This commit is contained in:
abnerhexu
2026-06-27 07:07:07 +00:00
parent a2e0126199
commit a32db39c80
38 changed files with 81187 additions and 19321 deletions
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69
generated-ooo/ALU.sv
View File

@@ -8,9 +8,15 @@ module ALU(
);
wire [5:0] shamt = io_isWord ? {1'h0, io_b[4:0]} : io_b[5:0];
wire [126:0] _raw_T_4 = {63'h0, io_a} << shamt;
wire [63:0] _GEN = {58'h0, shamt};
wire [64:0] _raw_T_22 =
wire [127:0] _GEN = {{64{io_a[63]}}, io_a};
wire [127:0] _signedProduct_T_2 = _GEN * {{64{io_b[63]}}, io_b};
wire [127:0] _GEN_0 = {64'h0, io_b};
wire [127:0] _signedUnsignedProduct_T_3 = _GEN * _GEN_0;
wire [127:0] unsignedProduct = {64'h0, io_a} * _GEN_0;
wire [126:0] _raw_T_5 = {63'h0, io_a} << shamt;
wire [31:0] _GEN_1 = {27'h0, io_b[4:0]};
wire [63:0] _GEN_2 = {58'h0, shamt};
wire [64:0] _raw_T_33 =
$unsigned($signed($signed({io_a[63], io_a}) / $signed({io_b[63], io_b})));
wire [63:0] raw =
io_fn == 5'h0
@@ -18,7 +24,7 @@ module ALU(
: io_fn == 5'h1
? io_a - io_b
: io_fn == 5'h2
? _raw_T_4[63:0]
? (io_isWord ? {1'h0, {31'h0, io_a[31:0]} << io_b[4:0]} : _raw_T_5[63:0])
: io_fn == 5'h3
? {63'h0, $signed(io_a) < $signed(io_b)}
: io_fn == 5'h4
@@ -26,35 +32,46 @@ module ALU(
: io_fn == 5'h5
? io_a ^ io_b
: io_fn == 5'h6
? io_a >> _GEN
? (io_isWord
? {32'h0, io_a[31:0] >> _GEN_1}
: io_a >> _GEN_2)
: io_fn == 5'h7
? $signed($signed(io_a) >>> _GEN)
? (io_isWord
? {32'h0, $signed($signed(io_a[31:0]) >>> _GEN_1)}
: $signed($signed(io_a) >>> _GEN_2))
: io_fn == 5'h8
? io_a | io_b
: io_fn == 5'h9
? io_a & io_b
: io_fn == 5'hA
? io_a * io_b
: io_fn == 5'hB
? ((|io_b)
? _raw_T_22[63:0]
: 64'hFFFFFFFFFFFFFFFF)
: io_fn == 5'hC
? ((|io_b)
? io_a / io_b
: 64'hFFFFFFFFFFFFFFFF)
: io_fn == 5'hD
? ((|io_b)
? $signed($signed(io_a)
% $signed(io_b))
: io_a)
: io_fn == 5'hE
? unsignedProduct[63:0]
: io_fn == 5'h10
? _signedProduct_T_2[127:64]
: io_fn == 5'h11
? _signedUnsignedProduct_T_3[127:64]
: io_fn == 5'h12
? unsignedProduct[127:64]
: io_fn == 5'hB
? ((|io_b)
? io_a % io_b
: io_a)
: io_fn == 5'hF
? io_b
: 64'h0;
? _raw_T_33[63:0]
: 64'hFFFFFFFFFFFFFFFF)
: io_fn == 5'hC
? ((|io_b)
? io_a / io_b
: 64'hFFFFFFFFFFFFFFFF)
: io_fn == 5'hD
? ((|io_b)
? $signed($signed(io_a)
% $signed(io_b))
: io_a)
: io_fn == 5'hE
? ((|io_b)
? io_a
% io_b
: io_a)
: io_fn == 5'hF
? io_b
: 64'h0;
assign io_out = io_isWord ? {{32{raw[31]}}, raw[31:0]} : raw;
endmodule

7
generated-ooo/CommitStage.sv
View File

@@ -13,6 +13,7 @@ module CommitStage(
input io_robEntry_0_branchMispredict,
input [63:0] io_robEntry_0_redirectPc,
input io_robEntry_0_csrValid,
io_robEntry_0_fenceI,
input [4:0] io_robEntry_1_archDest,
input io_robEntry_1_writesDest,
input [5:0] io_robEntry_1_dest,
@@ -23,6 +24,7 @@ module CommitStage(
input io_robEntry_1_branchMispredict,
input [63:0] io_robEntry_1_redirectPc,
input io_robEntry_1_csrValid,
io_robEntry_1_fenceI,
output io_commitReady_0,
io_commitReady_1,
io_freeOldPhys_0,
@@ -39,7 +41,8 @@ module CommitStage(
output [63:0] io_redirectPc,
output io_exception,
output [63:0] io_exceptionCause,
io_badAddr
io_badAddr,
output io_fenceI
);
wire firstTrap =
@@ -79,5 +82,7 @@ module CommitStage(
firstTrap
? io_robEntry_0_badAddr
: secondTrapSelected ? io_robEntry_1_badAddr : 64'h0;
assign io_fenceI =
io_robValid_0 & io_robEntry_0_fenceI | io_commitReady_1_0 & io_robEntry_1_fenceI;
endmodule

311
generated-ooo/Core.sv
View File

@@ -19,6 +19,7 @@ module Core(
wire _backend_io_decodeReady;
wire _backend_io_flush;
wire [63:0] _backend_io_redirectPc;
wire _backend_io_invalidateICache;
wire _id_io_outValid_0;
wire _id_io_outValid_1;
wire [63:0] _id_io_out_0_pc;
@@ -35,6 +36,7 @@ module Core(
wire [3:0] _id_io_out_0_opClass;
wire [4:0] _id_io_out_0_aluFn;
wire [2:0] _id_io_out_0_memWidth;
wire _id_io_out_0_memSigned;
wire _id_io_out_0_isLoad;
wire _id_io_out_0_isStore;
wire _id_io_out_0_isBranch;
@@ -45,6 +47,9 @@ module Core(
wire _id_io_out_0_isOpImm;
wire _id_io_out_0_isWord;
wire _id_io_out_0_isSystem;
wire _id_io_out_0_isFenceI;
wire _id_io_out_0_isAmo;
wire [4:0] _id_io_out_0_amoOp;
wire _id_io_out_0_writesRd;
wire _id_io_out_0_illegal;
wire [63:0] _id_io_out_1_pc;
@@ -61,6 +66,7 @@ module Core(
wire [3:0] _id_io_out_1_opClass;
wire [4:0] _id_io_out_1_aluFn;
wire [2:0] _id_io_out_1_memWidth;
wire _id_io_out_1_memSigned;
wire _id_io_out_1_isLoad;
wire _id_io_out_1_isStore;
wire _id_io_out_1_isBranch;
@@ -71,6 +77,9 @@ module Core(
wire _id_io_out_1_isOpImm;
wire _id_io_out_1_isWord;
wire _id_io_out_1_isSystem;
wire _id_io_out_1_isFenceI;
wire _id_io_out_1_isAmo;
wire [4:0] _id_io_out_1_amoOp;
wire _id_io_out_1_writesRd;
wire _id_io_out_1_illegal;
wire _frontend_io_outValid;
@@ -103,152 +112,170 @@ module Core(
end
end // always @(posedge)
Frontend frontend (
.clock (clock),
.reset (reset),
.io_redirectValid (_backend_io_flush),
.io_redirectPc (_backend_io_redirectPc),
.io_imemReqValid (io_imem_req_valid),
.io_imemReqAddr (io_imem_req_bits),
.io_imemRespValid (io_imem_resp_valid),
.io_imemRespBits_0 (io_imem_resp_bits_0),
.io_imemRespBits_1 (io_imem_resp_bits_1),
.io_outReady (fetchReady),
.io_outValid (_frontend_io_outValid),
.io_out_pc (_frontend_io_out_pc),
.io_out_inst_0 (_frontend_io_out_inst_0),
.io_out_inst_1 (_frontend_io_out_inst_1),
.io_out_laneValid_0 (_frontend_io_out_laneValid_0),
.io_out_laneValid_1 (_frontend_io_out_laneValid_1)
.clock (clock),
.reset (reset),
.io_redirectValid (_backend_io_flush),
.io_redirectPc (_backend_io_redirectPc),
.io_invalidateICache (_backend_io_invalidateICache),
.io_imemReqValid (io_imem_req_valid),
.io_imemReqAddr (io_imem_req_bits),
.io_imemRespValid (io_imem_resp_valid),
.io_imemRespBits_0 (io_imem_resp_bits_0),
.io_imemRespBits_1 (io_imem_resp_bits_1),
.io_outReady (fetchReady),
.io_outValid (_frontend_io_outValid),
.io_out_pc (_frontend_io_out_pc),
.io_out_inst_0 (_frontend_io_out_inst_0),
.io_out_inst_1 (_frontend_io_out_inst_1),
.io_out_laneValid_0 (_frontend_io_out_laneValid_0),
.io_out_laneValid_1 (_frontend_io_out_laneValid_1)
);
IDStage id (
.io_inValid (fetchValid),
.io_in_pc (fetchReg_pc),
.io_in_inst_0 (fetchReg_inst_0),
.io_in_inst_1 (fetchReg_inst_1),
.io_in_laneValid_0 (fetchReg_laneValid_0),
.io_in_laneValid_1 (fetchReg_laneValid_1),
.io_outValid_0 (_id_io_outValid_0),
.io_outValid_1 (_id_io_outValid_1),
.io_out_0_pc (_id_io_out_0_pc),
.io_out_0_inst (_id_io_out_0_inst),
.io_out_0_rs1 (_id_io_out_0_rs1),
.io_out_0_rs2 (_id_io_out_0_rs2),
.io_out_0_rd (_id_io_out_0_rd),
.io_out_0_funct3 (_id_io_out_0_funct3),
.io_out_0_immI (_id_io_out_0_immI),
.io_out_0_immS (_id_io_out_0_immS),
.io_out_0_immB (_id_io_out_0_immB),
.io_out_0_immU (_id_io_out_0_immU),
.io_out_0_immJ (_id_io_out_0_immJ),
.io_out_0_opClass (_id_io_out_0_opClass),
.io_out_0_aluFn (_id_io_out_0_aluFn),
.io_out_0_memWidth (_id_io_out_0_memWidth),
.io_out_0_isLoad (_id_io_out_0_isLoad),
.io_out_0_isStore (_id_io_out_0_isStore),
.io_out_0_isBranch (_id_io_out_0_isBranch),
.io_out_0_isJal (_id_io_out_0_isJal),
.io_out_0_isJalr (_id_io_out_0_isJalr),
.io_out_0_isLui (_id_io_out_0_isLui),
.io_out_0_isAuipc (_id_io_out_0_isAuipc),
.io_out_0_isOpImm (_id_io_out_0_isOpImm),
.io_out_0_isWord (_id_io_out_0_isWord),
.io_out_0_isSystem (_id_io_out_0_isSystem),
.io_out_0_writesRd (_id_io_out_0_writesRd),
.io_out_0_illegal (_id_io_out_0_illegal),
.io_out_1_pc (_id_io_out_1_pc),
.io_out_1_inst (_id_io_out_1_inst),
.io_out_1_rs1 (_id_io_out_1_rs1),
.io_out_1_rs2 (_id_io_out_1_rs2),
.io_out_1_rd (_id_io_out_1_rd),
.io_out_1_funct3 (_id_io_out_1_funct3),
.io_out_1_immI (_id_io_out_1_immI),
.io_out_1_immS (_id_io_out_1_immS),
.io_out_1_immB (_id_io_out_1_immB),
.io_out_1_immU (_id_io_out_1_immU),
.io_out_1_immJ (_id_io_out_1_immJ),
.io_out_1_opClass (_id_io_out_1_opClass),
.io_out_1_aluFn (_id_io_out_1_aluFn),
.io_out_1_memWidth (_id_io_out_1_memWidth),
.io_out_1_isLoad (_id_io_out_1_isLoad),
.io_out_1_isStore (_id_io_out_1_isStore),
.io_out_1_isBranch (_id_io_out_1_isBranch),
.io_out_1_isJal (_id_io_out_1_isJal),
.io_out_1_isJalr (_id_io_out_1_isJalr),
.io_out_1_isLui (_id_io_out_1_isLui),
.io_out_1_isAuipc (_id_io_out_1_isAuipc),
.io_out_1_isOpImm (_id_io_out_1_isOpImm),
.io_out_1_isWord (_id_io_out_1_isWord),
.io_out_1_isSystem (_id_io_out_1_isSystem),
.io_out_1_writesRd (_id_io_out_1_writesRd),
.io_out_1_illegal (_id_io_out_1_illegal)
.io_inValid (fetchValid),
.io_in_pc (fetchReg_pc),
.io_in_inst_0 (fetchReg_inst_0),
.io_in_inst_1 (fetchReg_inst_1),
.io_in_laneValid_0 (fetchReg_laneValid_0),
.io_in_laneValid_1 (fetchReg_laneValid_1),
.io_outValid_0 (_id_io_outValid_0),
.io_outValid_1 (_id_io_outValid_1),
.io_out_0_pc (_id_io_out_0_pc),
.io_out_0_inst (_id_io_out_0_inst),
.io_out_0_rs1 (_id_io_out_0_rs1),
.io_out_0_rs2 (_id_io_out_0_rs2),
.io_out_0_rd (_id_io_out_0_rd),
.io_out_0_funct3 (_id_io_out_0_funct3),
.io_out_0_immI (_id_io_out_0_immI),
.io_out_0_immS (_id_io_out_0_immS),
.io_out_0_immB (_id_io_out_0_immB),
.io_out_0_immU (_id_io_out_0_immU),
.io_out_0_immJ (_id_io_out_0_immJ),
.io_out_0_opClass (_id_io_out_0_opClass),
.io_out_0_aluFn (_id_io_out_0_aluFn),
.io_out_0_memWidth (_id_io_out_0_memWidth),
.io_out_0_memSigned (_id_io_out_0_memSigned),
.io_out_0_isLoad (_id_io_out_0_isLoad),
.io_out_0_isStore (_id_io_out_0_isStore),
.io_out_0_isBranch (_id_io_out_0_isBranch),
.io_out_0_isJal (_id_io_out_0_isJal),
.io_out_0_isJalr (_id_io_out_0_isJalr),
.io_out_0_isLui (_id_io_out_0_isLui),
.io_out_0_isAuipc (_id_io_out_0_isAuipc),
.io_out_0_isOpImm (_id_io_out_0_isOpImm),
.io_out_0_isWord (_id_io_out_0_isWord),
.io_out_0_isSystem (_id_io_out_0_isSystem),
.io_out_0_isFenceI (_id_io_out_0_isFenceI),
.io_out_0_isAmo (_id_io_out_0_isAmo),
.io_out_0_amoOp (_id_io_out_0_amoOp),
.io_out_0_writesRd (_id_io_out_0_writesRd),
.io_out_0_illegal (_id_io_out_0_illegal),
.io_out_1_pc (_id_io_out_1_pc),
.io_out_1_inst (_id_io_out_1_inst),
.io_out_1_rs1 (_id_io_out_1_rs1),
.io_out_1_rs2 (_id_io_out_1_rs2),
.io_out_1_rd (_id_io_out_1_rd),
.io_out_1_funct3 (_id_io_out_1_funct3),
.io_out_1_immI (_id_io_out_1_immI),
.io_out_1_immS (_id_io_out_1_immS),
.io_out_1_immB (_id_io_out_1_immB),
.io_out_1_immU (_id_io_out_1_immU),
.io_out_1_immJ (_id_io_out_1_immJ),
.io_out_1_opClass (_id_io_out_1_opClass),
.io_out_1_aluFn (_id_io_out_1_aluFn),
.io_out_1_memWidth (_id_io_out_1_memWidth),
.io_out_1_memSigned (_id_io_out_1_memSigned),
.io_out_1_isLoad (_id_io_out_1_isLoad),
.io_out_1_isStore (_id_io_out_1_isStore),
.io_out_1_isBranch (_id_io_out_1_isBranch),
.io_out_1_isJal (_id_io_out_1_isJal),
.io_out_1_isJalr (_id_io_out_1_isJalr),
.io_out_1_isLui (_id_io_out_1_isLui),
.io_out_1_isAuipc (_id_io_out_1_isAuipc),
.io_out_1_isOpImm (_id_io_out_1_isOpImm),
.io_out_1_isWord (_id_io_out_1_isWord),
.io_out_1_isSystem (_id_io_out_1_isSystem),
.io_out_1_isFenceI (_id_io_out_1_isFenceI),
.io_out_1_isAmo (_id_io_out_1_isAmo),
.io_out_1_amoOp (_id_io_out_1_amoOp),
.io_out_1_writesRd (_id_io_out_1_writesRd),
.io_out_1_illegal (_id_io_out_1_illegal)
);
OoOBackend backend (
.clock (clock),
.reset (reset),
.io_decodeValid_0 (_id_io_outValid_0),
.io_decodeValid_1 (_id_io_outValid_1),
.io_decode_0_pc (_id_io_out_0_pc),
.io_decode_0_inst (_id_io_out_0_inst),
.io_decode_0_rs1 (_id_io_out_0_rs1),
.io_decode_0_rs2 (_id_io_out_0_rs2),
.io_decode_0_rd (_id_io_out_0_rd),
.io_decode_0_funct3 (_id_io_out_0_funct3),
.io_decode_0_immI (_id_io_out_0_immI),
.io_decode_0_immS (_id_io_out_0_immS),
.io_decode_0_immB (_id_io_out_0_immB),
.io_decode_0_immU (_id_io_out_0_immU),
.io_decode_0_immJ (_id_io_out_0_immJ),
.io_decode_0_opClass (_id_io_out_0_opClass),
.io_decode_0_aluFn (_id_io_out_0_aluFn),
.io_decode_0_memWidth (_id_io_out_0_memWidth),
.io_decode_0_isLoad (_id_io_out_0_isLoad),
.io_decode_0_isStore (_id_io_out_0_isStore),
.io_decode_0_isBranch (_id_io_out_0_isBranch),
.io_decode_0_isJal (_id_io_out_0_isJal),
.io_decode_0_isJalr (_id_io_out_0_isJalr),
.io_decode_0_isLui (_id_io_out_0_isLui),
.io_decode_0_isAuipc (_id_io_out_0_isAuipc),
.io_decode_0_isOpImm (_id_io_out_0_isOpImm),
.io_decode_0_isWord (_id_io_out_0_isWord),
.io_decode_0_isSystem (_id_io_out_0_isSystem),
.io_decode_0_writesRd (_id_io_out_0_writesRd),
.io_decode_0_illegal (_id_io_out_0_illegal),
.io_decode_1_pc (_id_io_out_1_pc),
.io_decode_1_inst (_id_io_out_1_inst),
.io_decode_1_rs1 (_id_io_out_1_rs1),
.io_decode_1_rs2 (_id_io_out_1_rs2),
.io_decode_1_rd (_id_io_out_1_rd),
.io_decode_1_funct3 (_id_io_out_1_funct3),
.io_decode_1_immI (_id_io_out_1_immI),
.io_decode_1_immS (_id_io_out_1_immS),
.io_decode_1_immB (_id_io_out_1_immB),
.io_decode_1_immU (_id_io_out_1_immU),
.io_decode_1_immJ (_id_io_out_1_immJ),
.io_decode_1_opClass (_id_io_out_1_opClass),
.io_decode_1_aluFn (_id_io_out_1_aluFn),
.io_decode_1_memWidth (_id_io_out_1_memWidth),
.io_decode_1_isLoad (_id_io_out_1_isLoad),
.io_decode_1_isStore (_id_io_out_1_isStore),
.io_decode_1_isBranch (_id_io_out_1_isBranch),
.io_decode_1_isJal (_id_io_out_1_isJal),
.io_decode_1_isJalr (_id_io_out_1_isJalr),
.io_decode_1_isLui (_id_io_out_1_isLui),
.io_decode_1_isAuipc (_id_io_out_1_isAuipc),
.io_decode_1_isOpImm (_id_io_out_1_isOpImm),
.io_decode_1_isWord (_id_io_out_1_isWord),
.io_decode_1_isSystem (_id_io_out_1_isSystem),
.io_decode_1_writesRd (_id_io_out_1_writesRd),
.io_decode_1_illegal (_id_io_out_1_illegal),
.io_decodeReady (_backend_io_decodeReady),
.io_flush (_backend_io_flush),
.io_redirectPc (_backend_io_redirectPc),
.io_dmemReqValid (io_dmem_req_valid),
.io_dmemReq_addr (io_dmem_req_bits_addr),
.io_dmemReq_data (io_dmem_req_bits_data),
.io_dmemReq_isStore (io_dmem_req_bits_isStore),
.io_dmemReq_size (io_dmem_req_bits_size),
.io_dmemRespValid (io_dmem_resp_valid),
.io_dmemRespData (io_dmem_resp_bits)
.clock (clock),
.reset (reset),
.io_decodeValid_0 (_id_io_outValid_0),
.io_decodeValid_1 (_id_io_outValid_1),
.io_decode_0_pc (_id_io_out_0_pc),
.io_decode_0_inst (_id_io_out_0_inst),
.io_decode_0_rs1 (_id_io_out_0_rs1),
.io_decode_0_rs2 (_id_io_out_0_rs2),
.io_decode_0_rd (_id_io_out_0_rd),
.io_decode_0_funct3 (_id_io_out_0_funct3),
.io_decode_0_immI (_id_io_out_0_immI),
.io_decode_0_immS (_id_io_out_0_immS),
.io_decode_0_immB (_id_io_out_0_immB),
.io_decode_0_immU (_id_io_out_0_immU),
.io_decode_0_immJ (_id_io_out_0_immJ),
.io_decode_0_opClass (_id_io_out_0_opClass),
.io_decode_0_aluFn (_id_io_out_0_aluFn),
.io_decode_0_memWidth (_id_io_out_0_memWidth),
.io_decode_0_memSigned (_id_io_out_0_memSigned),
.io_decode_0_isLoad (_id_io_out_0_isLoad),
.io_decode_0_isStore (_id_io_out_0_isStore),
.io_decode_0_isBranch (_id_io_out_0_isBranch),
.io_decode_0_isJal (_id_io_out_0_isJal),
.io_decode_0_isJalr (_id_io_out_0_isJalr),
.io_decode_0_isLui (_id_io_out_0_isLui),
.io_decode_0_isAuipc (_id_io_out_0_isAuipc),
.io_decode_0_isOpImm (_id_io_out_0_isOpImm),
.io_decode_0_isWord (_id_io_out_0_isWord),
.io_decode_0_isSystem (_id_io_out_0_isSystem),
.io_decode_0_isFenceI (_id_io_out_0_isFenceI),
.io_decode_0_isAmo (_id_io_out_0_isAmo),
.io_decode_0_amoOp (_id_io_out_0_amoOp),
.io_decode_0_writesRd (_id_io_out_0_writesRd),
.io_decode_0_illegal (_id_io_out_0_illegal),
.io_decode_1_pc (_id_io_out_1_pc),
.io_decode_1_inst (_id_io_out_1_inst),
.io_decode_1_rs1 (_id_io_out_1_rs1),
.io_decode_1_rs2 (_id_io_out_1_rs2),
.io_decode_1_rd (_id_io_out_1_rd),
.io_decode_1_funct3 (_id_io_out_1_funct3),
.io_decode_1_immI (_id_io_out_1_immI),
.io_decode_1_immS (_id_io_out_1_immS),
.io_decode_1_immB (_id_io_out_1_immB),
.io_decode_1_immU (_id_io_out_1_immU),
.io_decode_1_immJ (_id_io_out_1_immJ),
.io_decode_1_opClass (_id_io_out_1_opClass),
.io_decode_1_aluFn (_id_io_out_1_aluFn),
.io_decode_1_memWidth (_id_io_out_1_memWidth),
.io_decode_1_memSigned (_id_io_out_1_memSigned),
.io_decode_1_isLoad (_id_io_out_1_isLoad),
.io_decode_1_isStore (_id_io_out_1_isStore),
.io_decode_1_isBranch (_id_io_out_1_isBranch),
.io_decode_1_isJal (_id_io_out_1_isJal),
.io_decode_1_isJalr (_id_io_out_1_isJalr),
.io_decode_1_isLui (_id_io_out_1_isLui),
.io_decode_1_isAuipc (_id_io_out_1_isAuipc),
.io_decode_1_isOpImm (_id_io_out_1_isOpImm),
.io_decode_1_isWord (_id_io_out_1_isWord),
.io_decode_1_isSystem (_id_io_out_1_isSystem),
.io_decode_1_isFenceI (_id_io_out_1_isFenceI),
.io_decode_1_isAmo (_id_io_out_1_isAmo),
.io_decode_1_amoOp (_id_io_out_1_amoOp),
.io_decode_1_writesRd (_id_io_out_1_writesRd),
.io_decode_1_illegal (_id_io_out_1_illegal),
.io_decodeReady (_backend_io_decodeReady),
.io_flush (_backend_io_flush),
.io_redirectPc (_backend_io_redirectPc),
.io_invalidateICache (_backend_io_invalidateICache),
.io_dmemReqValid (io_dmem_req_valid),
.io_dmemReq_addr (io_dmem_req_bits_addr),
.io_dmemReq_data (io_dmem_req_bits_data),
.io_dmemReq_isStore (io_dmem_req_bits_isStore),
.io_dmemReq_size (io_dmem_req_bits_size),
.io_dmemRespValid (io_dmem_resp_valid),
.io_dmemRespData (io_dmem_resp_bits)
);
endmodule

63503
generated-ooo/DCache.sv
View File

File diff suppressed because it is too large Load Diff

137
generated-ooo/Decoder.sv
View File

@@ -16,7 +16,8 @@ module Decoder(
output [3:0] io_out_opClass,
output [4:0] io_out_aluFn,
output [2:0] io_out_memWidth,
output io_out_isLoad,
output io_out_memSigned,
io_out_isLoad,
io_out_isStore,
io_out_isBranch,
io_out_isJal,
@@ -26,25 +27,30 @@ module Decoder(
io_out_isOpImm,
io_out_isWord,
io_out_isSystem,
io_out_writesRd,
io_out_isFenceI,
io_out_isAmo,
output [4:0] io_out_amoOp,
output io_out_writesRd,
io_out_illegal
);
wire [7:0][1:0] _GEN = '{2'h3, 2'h2, 2'h1, 2'h0, 2'h3, 2'h2, 2'h1, 2'h0};
wire [7:0][4:0] _GEN = '{5'hE, 5'hD, 5'hC, 5'hB, 5'h12, 5'h11, 5'h10, 5'hA};
wire [7:0][1:0] _GEN_0 = '{2'h3, 2'h2, 2'h1, 2'h0, 2'h3, 2'h2, 2'h1, 2'h0};
wire _d_isFenceI_T = io_inst[14:12] == 3'h1;
wire d_isLui = io_inst[6:0] == 7'h37;
wire _GEN_0 = io_inst[6:0] == 7'h17;
wire _GEN_1 = io_inst[6:0] == 7'h6F;
wire _GEN_2 = d_isLui | _GEN_0;
wire _GEN_3 = io_inst[6:0] == 7'h67;
wire _GEN_4 = io_inst[6:0] == 7'h63;
wire _GEN_5 = io_inst[6:0] == 7'h3;
wire _GEN_6 = io_inst[6:0] == 7'h23;
wire _GEN_1 = io_inst[6:0] == 7'h17;
wire _GEN_2 = io_inst[6:0] == 7'h6F;
wire _GEN_3 = d_isLui | _GEN_1;
wire _GEN_4 = io_inst[6:0] == 7'h67;
wire _GEN_5 = io_inst[6:0] == 7'h63;
wire _GEN_6 = io_inst[6:0] == 7'h3;
wire _GEN_7 = io_inst[6:0] == 7'h23;
wire _d_isWord_T = io_inst[6:0] == 7'h1B;
wire _GEN_7 = io_inst[6:0] == 7'h13 | _d_isWord_T;
wire _GEN_8 = _GEN_0 | _GEN_1 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6;
wire _GEN_9 = d_isLui | _GEN_8;
wire [4:0] _d_aluFn_T_3 = {3'h0, io_inst[14:12] == 3'h1, 1'h0};
wire [7:0][4:0] _GEN_10 =
wire _GEN_8 = io_inst[6:0] == 7'h13 | _d_isWord_T;
wire _GEN_9 = _GEN_1 | _GEN_2 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7;
wire _GEN_10 = d_isLui | _GEN_9;
wire [4:0] _d_aluFn_T_3 = {3'h0, _d_isFenceI_T, 1'h0};
wire [7:0][4:0] _GEN_11 =
{{5'h9},
{5'h8},
{{4'h3, io_inst[30]}},
@@ -54,8 +60,8 @@ module Decoder(
{_d_aluFn_T_3},
{_d_aluFn_T_3}};
wire _d_isWord_T_1 = io_inst[6:0] == 7'h3B;
wire _GEN_11 = io_inst[6:0] == 7'h33 | _d_isWord_T_1;
wire [7:0][4:0] _GEN_12 =
wire _GEN_12 = io_inst[6:0] == 7'h33 | _d_isWord_T_1;
wire [7:0][4:0] _GEN_13 =
{{5'h9},
{5'h8},
{{4'h3, io_inst[30]}},
@@ -64,13 +70,15 @@ module Decoder(
{5'h3},
{5'h2},
{{4'h0, io_inst[30]}}};
wire _GEN_13 = io_inst[6:0] == 7'hF;
wire _GEN_14 = io_inst[6:0] == 7'h73;
wire _GEN_15 = io_inst[6:0] == 7'h2F;
wire _GEN_16 = _GEN_13 | _GEN_14;
wire _GEN_17 = _GEN_7 | _GEN_11 | _GEN_16;
wire _GEN_18 = _GEN_6 | _GEN_17;
wire _GEN_19 = _GEN_1 | _GEN_3 | _GEN_4;
wire _GEN_14 = io_inst[6:0] == 7'hF;
wire _GEN_15 = _GEN_8 | _GEN_12;
wire _GEN_16 = io_inst[6:0] == 7'h73;
wire _GEN_17 = io_inst[6:0] == 7'h2F;
wire _GEN_18 = _GEN_14 | _GEN_16;
wire _GEN_19 = _GEN_7 | _GEN_8 | _GEN_12 | _GEN_18;
wire _GEN_20 = _GEN_2 | _GEN_4 | _GEN_5;
wire _GEN_21 =
d_isLui | _GEN_1 | _GEN_2 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_19;
assign io_out_pc = io_pc;
assign io_out_inst = io_inst;
assign io_out_rs1 = io_inst[19:15];
@@ -85,72 +93,67 @@ module Decoder(
assign io_out_immJ =
{{44{io_inst[31]}}, io_inst[19:12], io_inst[20], io_inst[30:21], 1'h0};
assign io_out_opClass =
_GEN_2
_GEN_3
? 4'h1
: _GEN_19
: _GEN_20
? 4'h2
: _GEN_5
: _GEN_6
? 4'h3
: _GEN_6
? 4'h4
: _GEN_7 | _GEN_11 ? 4'h1 : _GEN_16 ? 4'h5 : _GEN_15 ? 4'h3 : 4'h0;
: _GEN_7 ? 4'h4 : _GEN_15 ? 4'h1 : _GEN_18 ? 4'h5 : _GEN_17 ? 4'h3 : 4'h0;
assign io_out_aluFn =
d_isLui
? 5'hF
: _GEN_8
: _GEN_9
? 5'h0
: _GEN_7
? _GEN_10[io_inst[14:12]]
: _GEN_11
: _GEN_8
? _GEN_11[io_inst[14:12]]
: _GEN_12
? (io_inst[31:25] == 7'h1
? ((&(io_inst[14:12]))
? 5'hE
: io_inst[14:12] == 3'h6
? 5'hD
: io_inst[14:12] == 3'h5
? 5'hC
: {4'h5, io_inst[14:12] == 3'h4})
: _GEN_12[io_inst[14:12]])
? _GEN[io_inst[14:12]]
: _GEN_13[io_inst[14:12]])
: 5'h0;
assign io_out_memWidth =
d_isLui | _GEN_0 | _GEN_1 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_18 | ~_GEN_15
? {1'h0, _GEN[io_inst[14:12]]}
: {2'h1, io_inst[14:12] != 3'h2};
assign io_out_isLoad = ~(d_isLui | _GEN_0 | _GEN_19) & (_GEN_5 | ~_GEN_18 & _GEN_15);
_GEN_21 | ~_GEN_17 ? {1'h0, _GEN_0[io_inst[14:12]]} : {2'h1, io_inst[14:12] != 3'h2};
assign io_out_memSigned = ~(io_inst[14]);
assign io_out_isLoad = ~(d_isLui | _GEN_1 | _GEN_20) & (_GEN_6 | ~_GEN_19 & _GEN_17);
assign io_out_isStore =
~(d_isLui | _GEN_0 | _GEN_1 | _GEN_3 | _GEN_4 | _GEN_5)
& (_GEN_6 | ~_GEN_17 & _GEN_15);
assign io_out_isBranch = ~(d_isLui | _GEN_0 | _GEN_1 | _GEN_3) & _GEN_4;
assign io_out_isJal = ~_GEN_2 & _GEN_1;
assign io_out_isJalr = ~(d_isLui | _GEN_0 | _GEN_1) & _GEN_3;
~(d_isLui | _GEN_1 | _GEN_2 | _GEN_4 | _GEN_5 | _GEN_6) & _GEN_7;
assign io_out_isBranch = ~(d_isLui | _GEN_1 | _GEN_2 | _GEN_4) & _GEN_5;
assign io_out_isJal = ~_GEN_3 & _GEN_2;
assign io_out_isJalr = ~(d_isLui | _GEN_1 | _GEN_2) & _GEN_4;
assign io_out_isLui = d_isLui;
assign io_out_isAuipc = ~d_isLui & _GEN_0;
assign io_out_isOpImm = ~_GEN_9 & _GEN_7;
assign io_out_isWord = ~_GEN_9 & (_GEN_7 ? _d_isWord_T : _GEN_11 & _d_isWord_T_1);
assign io_out_isAuipc = ~d_isLui & _GEN_1;
assign io_out_isOpImm = ~_GEN_10 & _GEN_8;
assign io_out_isWord = ~_GEN_10 & (_GEN_8 ? _d_isWord_T : _GEN_12 & _d_isWord_T_1);
assign io_out_isSystem =
~(d_isLui | _GEN_0 | _GEN_1 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_11
| _GEN_13) & _GEN_14;
~(d_isLui | _GEN_1 | _GEN_2 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_8 | _GEN_12
| _GEN_14) & _GEN_16;
assign io_out_isFenceI =
~(d_isLui | _GEN_1 | _GEN_2 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 | _GEN_15) & _GEN_14
& _d_isFenceI_T;
assign io_out_isAmo = ~_GEN_21 & _GEN_17;
assign io_out_amoOp = io_inst[31:27];
assign io_out_writesRd =
d_isLui
? (|(io_inst[11:7]))
: _GEN_0
: _GEN_1
? (|(io_inst[11:7]))
: _GEN_1
: _GEN_2
? (|(io_inst[11:7]))
: _GEN_3
: _GEN_4
? (|(io_inst[11:7]))
: ~_GEN_4
& (_GEN_5
: ~_GEN_5
& (_GEN_6
? (|(io_inst[11:7]))
: ~_GEN_6
& (_GEN_7
: ~_GEN_7
& (_GEN_8
? (|(io_inst[11:7]))
: _GEN_11
: _GEN_12
? (|(io_inst[11:7]))
: ~_GEN_13
& (_GEN_14
: ~_GEN_14
& (_GEN_16
? (|(io_inst[11:7])) & (|(io_inst[14:12]))
: _GEN_15 & (|(io_inst[11:7])))));
: _GEN_17 & (|(io_inst[11:7])))));
assign io_out_illegal =
io_inst[6:0] != 7'h37 & io_inst[6:0] != 7'h17 & io_inst[6:0] != 7'h6F
& io_inst[6:0] != 7'h67 & io_inst[6:0] != 7'h63 & io_inst[6:0] != 7'h3

2
generated-ooo/Frontend.sv
View File

@@ -4,6 +4,7 @@ module Frontend(
reset,
io_redirectValid,
input [63:0] io_redirectPc,
input io_invalidateICache,
output io_imemReqValid,
output [63:0] io_imemReqAddr,
input io_imemRespValid,
@@ -41,6 +42,7 @@ module Frontend(
.io_reqAddr (pc),
.io_reqPc (pc),
.io_flush (io_redirectValid),
.io_invalidate (io_invalidateICache),
.io_respReady (io_outReady),
.io_memReqValid (io_imemReqValid),
.io_memReqAddr (io_imemReqAddr),

26759
generated-ooo/ICache.sv
View File

File diff suppressed because it is too large Load Diff

136
generated-ooo/IDStage.sv
View File

@@ -22,7 +22,8 @@ module IDStage(
output [3:0] io_out_0_opClass,
output [4:0] io_out_0_aluFn,
output [2:0] io_out_0_memWidth,
output io_out_0_isLoad,
output io_out_0_memSigned,
io_out_0_isLoad,
io_out_0_isStore,
io_out_0_isBranch,
io_out_0_isJal,
@@ -32,7 +33,10 @@ module IDStage(
io_out_0_isOpImm,
io_out_0_isWord,
io_out_0_isSystem,
io_out_0_writesRd,
io_out_0_isFenceI,
io_out_0_isAmo,
output [4:0] io_out_0_amoOp,
output io_out_0_writesRd,
io_out_0_illegal,
output [63:0] io_out_1_pc,
output [31:0] io_out_1_inst,
@@ -48,7 +52,8 @@ module IDStage(
output [3:0] io_out_1_opClass,
output [4:0] io_out_1_aluFn,
output [2:0] io_out_1_memWidth,
output io_out_1_isLoad,
output io_out_1_memSigned,
io_out_1_isLoad,
io_out_1_isStore,
io_out_1_isBranch,
io_out_1_isJal,
@@ -58,69 +63,80 @@ module IDStage(
io_out_1_isOpImm,
io_out_1_isWord,
io_out_1_isSystem,
io_out_1_writesRd,
io_out_1_isFenceI,
io_out_1_isAmo,
output [4:0] io_out_1_amoOp,
output io_out_1_writesRd,
io_out_1_illegal
);
Decoder decoders_0 (
.io_pc (io_in_pc),
.io_inst (io_in_inst_0),
.io_out_pc (io_out_0_pc),
.io_out_inst (io_out_0_inst),
.io_out_rs1 (io_out_0_rs1),
.io_out_rs2 (io_out_0_rs2),
.io_out_rd (io_out_0_rd),
.io_out_funct3 (io_out_0_funct3),
.io_out_immI (io_out_0_immI),
.io_out_immS (io_out_0_immS),
.io_out_immB (io_out_0_immB),
.io_out_immU (io_out_0_immU),
.io_out_immJ (io_out_0_immJ),
.io_out_opClass (io_out_0_opClass),
.io_out_aluFn (io_out_0_aluFn),
.io_out_memWidth (io_out_0_memWidth),
.io_out_isLoad (io_out_0_isLoad),
.io_out_isStore (io_out_0_isStore),
.io_out_isBranch (io_out_0_isBranch),
.io_out_isJal (io_out_0_isJal),
.io_out_isJalr (io_out_0_isJalr),
.io_out_isLui (io_out_0_isLui),
.io_out_isAuipc (io_out_0_isAuipc),
.io_out_isOpImm (io_out_0_isOpImm),
.io_out_isWord (io_out_0_isWord),
.io_out_isSystem (io_out_0_isSystem),
.io_out_writesRd (io_out_0_writesRd),
.io_out_illegal (io_out_0_illegal)
.io_pc (io_in_pc),
.io_inst (io_in_inst_0),
.io_out_pc (io_out_0_pc),
.io_out_inst (io_out_0_inst),
.io_out_rs1 (io_out_0_rs1),
.io_out_rs2 (io_out_0_rs2),
.io_out_rd (io_out_0_rd),
.io_out_funct3 (io_out_0_funct3),
.io_out_immI (io_out_0_immI),
.io_out_immS (io_out_0_immS),
.io_out_immB (io_out_0_immB),
.io_out_immU (io_out_0_immU),
.io_out_immJ (io_out_0_immJ),
.io_out_opClass (io_out_0_opClass),
.io_out_aluFn (io_out_0_aluFn),
.io_out_memWidth (io_out_0_memWidth),
.io_out_memSigned (io_out_0_memSigned),
.io_out_isLoad (io_out_0_isLoad),
.io_out_isStore (io_out_0_isStore),
.io_out_isBranch (io_out_0_isBranch),
.io_out_isJal (io_out_0_isJal),
.io_out_isJalr (io_out_0_isJalr),
.io_out_isLui (io_out_0_isLui),
.io_out_isAuipc (io_out_0_isAuipc),
.io_out_isOpImm (io_out_0_isOpImm),
.io_out_isWord (io_out_0_isWord),
.io_out_isSystem (io_out_0_isSystem),
.io_out_isFenceI (io_out_0_isFenceI),
.io_out_isAmo (io_out_0_isAmo),
.io_out_amoOp (io_out_0_amoOp),
.io_out_writesRd (io_out_0_writesRd),
.io_out_illegal (io_out_0_illegal)
);
Decoder decoders_1 (
.io_pc (io_in_pc + 64'h4),
.io_inst (io_in_inst_1),
.io_out_pc (io_out_1_pc),
.io_out_inst (io_out_1_inst),
.io_out_rs1 (io_out_1_rs1),
.io_out_rs2 (io_out_1_rs2),
.io_out_rd (io_out_1_rd),
.io_out_funct3 (io_out_1_funct3),
.io_out_immI (io_out_1_immI),
.io_out_immS (io_out_1_immS),
.io_out_immB (io_out_1_immB),
.io_out_immU (io_out_1_immU),
.io_out_immJ (io_out_1_immJ),
.io_out_opClass (io_out_1_opClass),
.io_out_aluFn (io_out_1_aluFn),
.io_out_memWidth (io_out_1_memWidth),
.io_out_isLoad (io_out_1_isLoad),
.io_out_isStore (io_out_1_isStore),
.io_out_isBranch (io_out_1_isBranch),
.io_out_isJal (io_out_1_isJal),
.io_out_isJalr (io_out_1_isJalr),
.io_out_isLui (io_out_1_isLui),
.io_out_isAuipc (io_out_1_isAuipc),
.io_out_isOpImm (io_out_1_isOpImm),
.io_out_isWord (io_out_1_isWord),
.io_out_isSystem (io_out_1_isSystem),
.io_out_writesRd (io_out_1_writesRd),
.io_out_illegal (io_out_1_illegal)
.io_pc (io_in_pc + 64'h4),
.io_inst (io_in_inst_1),
.io_out_pc (io_out_1_pc),
.io_out_inst (io_out_1_inst),
.io_out_rs1 (io_out_1_rs1),
.io_out_rs2 (io_out_1_rs2),
.io_out_rd (io_out_1_rd),
.io_out_funct3 (io_out_1_funct3),
.io_out_immI (io_out_1_immI),
.io_out_immS (io_out_1_immS),
.io_out_immB (io_out_1_immB),
.io_out_immU (io_out_1_immU),
.io_out_immJ (io_out_1_immJ),
.io_out_opClass (io_out_1_opClass),
.io_out_aluFn (io_out_1_aluFn),
.io_out_memWidth (io_out_1_memWidth),
.io_out_memSigned (io_out_1_memSigned),
.io_out_isLoad (io_out_1_isLoad),
.io_out_isStore (io_out_1_isStore),
.io_out_isBranch (io_out_1_isBranch),
.io_out_isJal (io_out_1_isJal),
.io_out_isJalr (io_out_1_isJalr),
.io_out_isLui (io_out_1_isLui),
.io_out_isAuipc (io_out_1_isAuipc),
.io_out_isOpImm (io_out_1_isOpImm),
.io_out_isWord (io_out_1_isWord),
.io_out_isSystem (io_out_1_isSystem),
.io_out_isFenceI (io_out_1_isFenceI),
.io_out_isAmo (io_out_1_isAmo),
.io_out_amoOp (io_out_1_amoOp),
.io_out_writesRd (io_out_1_writesRd),
.io_out_illegal (io_out_1_illegal)
);
assign io_outValid_0 = io_inValid & io_in_laneValid_0;
assign io_outValid_1 = io_inValid & io_in_laneValid_1;

306
generated-ooo/IssueQueue.sv
View File

@@ -16,7 +16,8 @@ module IssueQueue(
io_enq_0_decoded_immJ,
input [4:0] io_enq_0_decoded_aluFn,
input [2:0] io_enq_0_decoded_memWidth,
input io_enq_0_decoded_isLoad,
input io_enq_0_decoded_memSigned,
io_enq_0_decoded_isLoad,
io_enq_0_decoded_isStore,
io_enq_0_decoded_isBranch,
io_enq_0_decoded_isJal,
@@ -26,7 +27,10 @@ module IssueQueue(
io_enq_0_decoded_isOpImm,
io_enq_0_decoded_isWord,
io_enq_0_decoded_isSystem,
io_enq_0_decoded_writesRd,
io_enq_0_decoded_isFenceI,
io_enq_0_decoded_isAmo,
input [4:0] io_enq_0_decoded_amoOp,
input io_enq_0_decoded_writesRd,
io_enq_0_decoded_illegal,
input [5:0] io_enq_0_prs1,
io_enq_0_prs2,
@@ -46,7 +50,8 @@ module IssueQueue(
io_enq_1_decoded_immJ,
input [4:0] io_enq_1_decoded_aluFn,
input [2:0] io_enq_1_decoded_memWidth,
input io_enq_1_decoded_isLoad,
input io_enq_1_decoded_memSigned,
io_enq_1_decoded_isLoad,
io_enq_1_decoded_isStore,
io_enq_1_decoded_isBranch,
io_enq_1_decoded_isJal,
@@ -56,7 +61,10 @@ module IssueQueue(
io_enq_1_decoded_isOpImm,
io_enq_1_decoded_isWord,
io_enq_1_decoded_isSystem,
io_enq_1_decoded_writesRd,
io_enq_1_decoded_isFenceI,
io_enq_1_decoded_isAmo,
input [4:0] io_enq_1_decoded_amoOp,
input io_enq_1_decoded_writesRd,
io_enq_1_decoded_illegal,
input [5:0] io_enq_1_prs1,
io_enq_1_prs2,
@@ -83,7 +91,8 @@ module IssueQueue(
io_issue_0_decoded_immJ,
output [4:0] io_issue_0_decoded_aluFn,
output [2:0] io_issue_0_decoded_memWidth,
output io_issue_0_decoded_isLoad,
output io_issue_0_decoded_memSigned,
io_issue_0_decoded_isLoad,
io_issue_0_decoded_isStore,
io_issue_0_decoded_isBranch,
io_issue_0_decoded_isJal,
@@ -93,7 +102,10 @@ module IssueQueue(
io_issue_0_decoded_isOpImm,
io_issue_0_decoded_isWord,
io_issue_0_decoded_isSystem,
io_issue_0_decoded_writesRd,
io_issue_0_decoded_isFenceI,
io_issue_0_decoded_isAmo,
output [4:0] io_issue_0_decoded_amoOp,
output io_issue_0_decoded_writesRd,
io_issue_0_decoded_illegal,
output [5:0] io_issue_0_prs1,
io_issue_0_prs2,
@@ -110,7 +122,8 @@ module IssueQueue(
io_issue_1_decoded_immJ,
output [4:0] io_issue_1_decoded_aluFn,
output [2:0] io_issue_1_decoded_memWidth,
output io_issue_1_decoded_isLoad,
output io_issue_1_decoded_memSigned,
io_issue_1_decoded_isLoad,
io_issue_1_decoded_isStore,
io_issue_1_decoded_isBranch,
io_issue_1_decoded_isJal,
@@ -120,7 +133,10 @@ module IssueQueue(
io_issue_1_decoded_isOpImm,
io_issue_1_decoded_isWord,
io_issue_1_decoded_isSystem,
io_issue_1_decoded_writesRd,
io_issue_1_decoded_isFenceI,
io_issue_1_decoded_isAmo,
output [4:0] io_issue_1_decoded_amoOp,
output io_issue_1_decoded_writesRd,
io_issue_1_decoded_illegal,
output [5:0] io_issue_1_prs1,
io_issue_1_prs2,
@@ -132,135 +148,151 @@ module IssueQueue(
);
ReservationStation intRs (
.clock (clock),
.reset (reset),
.io_enqValid_0 (io_enqValid_0),
.io_enqValid_1 (io_enqValid_1),
.io_enq_0_decoded_pc (io_enq_0_decoded_pc),
.io_enq_0_decoded_inst (io_enq_0_decoded_inst),
.io_enq_0_decoded_rs1 (io_enq_0_decoded_rs1),
.io_enq_0_decoded_rs2 (io_enq_0_decoded_rs2),
.io_enq_0_decoded_funct3 (io_enq_0_decoded_funct3),
.io_enq_0_decoded_immI (io_enq_0_decoded_immI),
.io_enq_0_decoded_immS (io_enq_0_decoded_immS),
.io_enq_0_decoded_immB (io_enq_0_decoded_immB),
.io_enq_0_decoded_immU (io_enq_0_decoded_immU),
.io_enq_0_decoded_immJ (io_enq_0_decoded_immJ),
.io_enq_0_decoded_aluFn (io_enq_0_decoded_aluFn),
.io_enq_0_decoded_memWidth (io_enq_0_decoded_memWidth),
.io_enq_0_decoded_isLoad (io_enq_0_decoded_isLoad),
.io_enq_0_decoded_isStore (io_enq_0_decoded_isStore),
.io_enq_0_decoded_isBranch (io_enq_0_decoded_isBranch),
.io_enq_0_decoded_isJal (io_enq_0_decoded_isJal),
.io_enq_0_decoded_isJalr (io_enq_0_decoded_isJalr),
.io_enq_0_decoded_isLui (io_enq_0_decoded_isLui),
.io_enq_0_decoded_isAuipc (io_enq_0_decoded_isAuipc),
.io_enq_0_decoded_isOpImm (io_enq_0_decoded_isOpImm),
.io_enq_0_decoded_isWord (io_enq_0_decoded_isWord),
.io_enq_0_decoded_isSystem (io_enq_0_decoded_isSystem),
.io_enq_0_decoded_writesRd (io_enq_0_decoded_writesRd),
.io_enq_0_decoded_illegal (io_enq_0_decoded_illegal),
.io_enq_0_prs1 (io_enq_0_prs1),
.io_enq_0_prs2 (io_enq_0_prs2),
.io_enq_0_src1Ready (io_enq_0_src1Ready),
.io_enq_0_src2Ready (io_enq_0_src2Ready),
.io_enq_0_prd (io_enq_0_prd),
.io_enq_0_robIdx (io_enq_0_robIdx),
.io_enq_1_decoded_pc (io_enq_1_decoded_pc),
.io_enq_1_decoded_inst (io_enq_1_decoded_inst),
.io_enq_1_decoded_rs1 (io_enq_1_decoded_rs1),
.io_enq_1_decoded_rs2 (io_enq_1_decoded_rs2),
.io_enq_1_decoded_funct3 (io_enq_1_decoded_funct3),
.io_enq_1_decoded_immI (io_enq_1_decoded_immI),
.io_enq_1_decoded_immS (io_enq_1_decoded_immS),
.io_enq_1_decoded_immB (io_enq_1_decoded_immB),
.io_enq_1_decoded_immU (io_enq_1_decoded_immU),
.io_enq_1_decoded_immJ (io_enq_1_decoded_immJ),
.io_enq_1_decoded_aluFn (io_enq_1_decoded_aluFn),
.io_enq_1_decoded_memWidth (io_enq_1_decoded_memWidth),
.io_enq_1_decoded_isLoad (io_enq_1_decoded_isLoad),
.io_enq_1_decoded_isStore (io_enq_1_decoded_isStore),
.io_enq_1_decoded_isBranch (io_enq_1_decoded_isBranch),
.io_enq_1_decoded_isJal (io_enq_1_decoded_isJal),
.io_enq_1_decoded_isJalr (io_enq_1_decoded_isJalr),
.io_enq_1_decoded_isLui (io_enq_1_decoded_isLui),
.io_enq_1_decoded_isAuipc (io_enq_1_decoded_isAuipc),
.io_enq_1_decoded_isOpImm (io_enq_1_decoded_isOpImm),
.io_enq_1_decoded_isWord (io_enq_1_decoded_isWord),
.io_enq_1_decoded_isSystem (io_enq_1_decoded_isSystem),
.io_enq_1_decoded_writesRd (io_enq_1_decoded_writesRd),
.io_enq_1_decoded_illegal (io_enq_1_decoded_illegal),
.io_enq_1_prs1 (io_enq_1_prs1),
.io_enq_1_prs2 (io_enq_1_prs2),
.io_enq_1_src1Ready (io_enq_1_src1Ready),
.io_enq_1_src2Ready (io_enq_1_src2Ready),
.io_enq_1_prd (io_enq_1_prd),
.io_enq_1_robIdx (io_enq_1_robIdx),
.io_enqReady_0 (io_enqReady_0),
.io_enqReady_1 (io_enqReady_1),
.io_wakeup_0_valid (io_wakeup_0_valid),
.io_wakeup_0_phys (io_wakeup_0_phys),
.io_wakeup_1_valid (io_wakeup_1_valid),
.io_wakeup_1_phys (io_wakeup_1_phys),
.io_issueValid_0 (io_issueValid_0),
.io_issueValid_1 (io_issueValid_1),
.io_issue_0_decoded_pc (io_issue_0_decoded_pc),
.io_issue_0_decoded_inst (io_issue_0_decoded_inst),
.io_issue_0_decoded_rs1 (io_issue_0_decoded_rs1),
.io_issue_0_decoded_funct3 (io_issue_0_decoded_funct3),
.io_issue_0_decoded_immI (io_issue_0_decoded_immI),
.io_issue_0_decoded_immS (io_issue_0_decoded_immS),
.io_issue_0_decoded_immB (io_issue_0_decoded_immB),
.io_issue_0_decoded_immU (io_issue_0_decoded_immU),
.io_issue_0_decoded_immJ (io_issue_0_decoded_immJ),
.io_issue_0_decoded_aluFn (io_issue_0_decoded_aluFn),
.io_issue_0_decoded_memWidth (io_issue_0_decoded_memWidth),
.io_issue_0_decoded_isLoad (io_issue_0_decoded_isLoad),
.io_issue_0_decoded_isStore (io_issue_0_decoded_isStore),
.io_issue_0_decoded_isBranch (io_issue_0_decoded_isBranch),
.io_issue_0_decoded_isJal (io_issue_0_decoded_isJal),
.io_issue_0_decoded_isJalr (io_issue_0_decoded_isJalr),
.io_issue_0_decoded_isLui (io_issue_0_decoded_isLui),
.io_issue_0_decoded_isAuipc (io_issue_0_decoded_isAuipc),
.io_issue_0_decoded_isOpImm (io_issue_0_decoded_isOpImm),
.io_issue_0_decoded_isWord (io_issue_0_decoded_isWord),
.io_issue_0_decoded_isSystem (io_issue_0_decoded_isSystem),
.io_issue_0_decoded_writesRd (io_issue_0_decoded_writesRd),
.io_issue_0_decoded_illegal (io_issue_0_decoded_illegal),
.io_issue_0_prs1 (io_issue_0_prs1),
.io_issue_0_prs2 (io_issue_0_prs2),
.io_issue_0_prd (io_issue_0_prd),
.io_issue_0_robIdx (io_issue_0_robIdx),
.io_issue_1_decoded_pc (io_issue_1_decoded_pc),
.io_issue_1_decoded_inst (io_issue_1_decoded_inst),
.io_issue_1_decoded_rs1 (io_issue_1_decoded_rs1),
.io_issue_1_decoded_funct3 (io_issue_1_decoded_funct3),
.io_issue_1_decoded_immI (io_issue_1_decoded_immI),
.io_issue_1_decoded_immS (io_issue_1_decoded_immS),
.io_issue_1_decoded_immB (io_issue_1_decoded_immB),
.io_issue_1_decoded_immU (io_issue_1_decoded_immU),
.io_issue_1_decoded_immJ (io_issue_1_decoded_immJ),
.io_issue_1_decoded_aluFn (io_issue_1_decoded_aluFn),
.io_issue_1_decoded_memWidth (io_issue_1_decoded_memWidth),
.io_issue_1_decoded_isLoad (io_issue_1_decoded_isLoad),
.io_issue_1_decoded_isStore (io_issue_1_decoded_isStore),
.io_issue_1_decoded_isBranch (io_issue_1_decoded_isBranch),
.io_issue_1_decoded_isJal (io_issue_1_decoded_isJal),
.io_issue_1_decoded_isJalr (io_issue_1_decoded_isJalr),
.io_issue_1_decoded_isLui (io_issue_1_decoded_isLui),
.io_issue_1_decoded_isAuipc (io_issue_1_decoded_isAuipc),
.io_issue_1_decoded_isOpImm (io_issue_1_decoded_isOpImm),
.io_issue_1_decoded_isWord (io_issue_1_decoded_isWord),
.io_issue_1_decoded_isSystem (io_issue_1_decoded_isSystem),
.io_issue_1_decoded_writesRd (io_issue_1_decoded_writesRd),
.io_issue_1_decoded_illegal (io_issue_1_decoded_illegal),
.io_issue_1_prs1 (io_issue_1_prs1),
.io_issue_1_prs2 (io_issue_1_prs2),
.io_issue_1_prd (io_issue_1_prd),
.io_issue_1_robIdx (io_issue_1_robIdx),
.io_issueReady_0 (io_issueReady_0),
.io_issueReady_1 (io_issueReady_1),
.io_flush (io_flush)
.clock (clock),
.reset (reset),
.io_enqValid_0 (io_enqValid_0),
.io_enqValid_1 (io_enqValid_1),
.io_enq_0_decoded_pc (io_enq_0_decoded_pc),
.io_enq_0_decoded_inst (io_enq_0_decoded_inst),
.io_enq_0_decoded_rs1 (io_enq_0_decoded_rs1),
.io_enq_0_decoded_rs2 (io_enq_0_decoded_rs2),
.io_enq_0_decoded_funct3 (io_enq_0_decoded_funct3),
.io_enq_0_decoded_immI (io_enq_0_decoded_immI),
.io_enq_0_decoded_immS (io_enq_0_decoded_immS),
.io_enq_0_decoded_immB (io_enq_0_decoded_immB),
.io_enq_0_decoded_immU (io_enq_0_decoded_immU),
.io_enq_0_decoded_immJ (io_enq_0_decoded_immJ),
.io_enq_0_decoded_aluFn (io_enq_0_decoded_aluFn),
.io_enq_0_decoded_memWidth (io_enq_0_decoded_memWidth),
.io_enq_0_decoded_memSigned (io_enq_0_decoded_memSigned),
.io_enq_0_decoded_isLoad (io_enq_0_decoded_isLoad),
.io_enq_0_decoded_isStore (io_enq_0_decoded_isStore),
.io_enq_0_decoded_isBranch (io_enq_0_decoded_isBranch),
.io_enq_0_decoded_isJal (io_enq_0_decoded_isJal),
.io_enq_0_decoded_isJalr (io_enq_0_decoded_isJalr),
.io_enq_0_decoded_isLui (io_enq_0_decoded_isLui),
.io_enq_0_decoded_isAuipc (io_enq_0_decoded_isAuipc),
.io_enq_0_decoded_isOpImm (io_enq_0_decoded_isOpImm),
.io_enq_0_decoded_isWord (io_enq_0_decoded_isWord),
.io_enq_0_decoded_isSystem (io_enq_0_decoded_isSystem),
.io_enq_0_decoded_isFenceI (io_enq_0_decoded_isFenceI),
.io_enq_0_decoded_isAmo (io_enq_0_decoded_isAmo),
.io_enq_0_decoded_amoOp (io_enq_0_decoded_amoOp),
.io_enq_0_decoded_writesRd (io_enq_0_decoded_writesRd),
.io_enq_0_decoded_illegal (io_enq_0_decoded_illegal),
.io_enq_0_prs1 (io_enq_0_prs1),
.io_enq_0_prs2 (io_enq_0_prs2),
.io_enq_0_src1Ready (io_enq_0_src1Ready),
.io_enq_0_src2Ready (io_enq_0_src2Ready),
.io_enq_0_prd (io_enq_0_prd),
.io_enq_0_robIdx (io_enq_0_robIdx),
.io_enq_1_decoded_pc (io_enq_1_decoded_pc),
.io_enq_1_decoded_inst (io_enq_1_decoded_inst),
.io_enq_1_decoded_rs1 (io_enq_1_decoded_rs1),
.io_enq_1_decoded_rs2 (io_enq_1_decoded_rs2),
.io_enq_1_decoded_funct3 (io_enq_1_decoded_funct3),
.io_enq_1_decoded_immI (io_enq_1_decoded_immI),
.io_enq_1_decoded_immS (io_enq_1_decoded_immS),
.io_enq_1_decoded_immB (io_enq_1_decoded_immB),
.io_enq_1_decoded_immU (io_enq_1_decoded_immU),
.io_enq_1_decoded_immJ (io_enq_1_decoded_immJ),
.io_enq_1_decoded_aluFn (io_enq_1_decoded_aluFn),
.io_enq_1_decoded_memWidth (io_enq_1_decoded_memWidth),
.io_enq_1_decoded_memSigned (io_enq_1_decoded_memSigned),
.io_enq_1_decoded_isLoad (io_enq_1_decoded_isLoad),
.io_enq_1_decoded_isStore (io_enq_1_decoded_isStore),
.io_enq_1_decoded_isBranch (io_enq_1_decoded_isBranch),
.io_enq_1_decoded_isJal (io_enq_1_decoded_isJal),
.io_enq_1_decoded_isJalr (io_enq_1_decoded_isJalr),
.io_enq_1_decoded_isLui (io_enq_1_decoded_isLui),
.io_enq_1_decoded_isAuipc (io_enq_1_decoded_isAuipc),
.io_enq_1_decoded_isOpImm (io_enq_1_decoded_isOpImm),
.io_enq_1_decoded_isWord (io_enq_1_decoded_isWord),
.io_enq_1_decoded_isSystem (io_enq_1_decoded_isSystem),
.io_enq_1_decoded_isFenceI (io_enq_1_decoded_isFenceI),
.io_enq_1_decoded_isAmo (io_enq_1_decoded_isAmo),
.io_enq_1_decoded_amoOp (io_enq_1_decoded_amoOp),
.io_enq_1_decoded_writesRd (io_enq_1_decoded_writesRd),
.io_enq_1_decoded_illegal (io_enq_1_decoded_illegal),
.io_enq_1_prs1 (io_enq_1_prs1),
.io_enq_1_prs2 (io_enq_1_prs2),
.io_enq_1_src1Ready (io_enq_1_src1Ready),
.io_enq_1_src2Ready (io_enq_1_src2Ready),
.io_enq_1_prd (io_enq_1_prd),
.io_enq_1_robIdx (io_enq_1_robIdx),
.io_enqReady_0 (io_enqReady_0),
.io_enqReady_1 (io_enqReady_1),
.io_wakeup_0_valid (io_wakeup_0_valid),
.io_wakeup_0_phys (io_wakeup_0_phys),
.io_wakeup_1_valid (io_wakeup_1_valid),
.io_wakeup_1_phys (io_wakeup_1_phys),
.io_issueValid_0 (io_issueValid_0),
.io_issueValid_1 (io_issueValid_1),
.io_issue_0_decoded_pc (io_issue_0_decoded_pc),
.io_issue_0_decoded_inst (io_issue_0_decoded_inst),
.io_issue_0_decoded_rs1 (io_issue_0_decoded_rs1),
.io_issue_0_decoded_funct3 (io_issue_0_decoded_funct3),
.io_issue_0_decoded_immI (io_issue_0_decoded_immI),
.io_issue_0_decoded_immS (io_issue_0_decoded_immS),
.io_issue_0_decoded_immB (io_issue_0_decoded_immB),
.io_issue_0_decoded_immU (io_issue_0_decoded_immU),
.io_issue_0_decoded_immJ (io_issue_0_decoded_immJ),
.io_issue_0_decoded_aluFn (io_issue_0_decoded_aluFn),
.io_issue_0_decoded_memWidth (io_issue_0_decoded_memWidth),
.io_issue_0_decoded_memSigned (io_issue_0_decoded_memSigned),
.io_issue_0_decoded_isLoad (io_issue_0_decoded_isLoad),
.io_issue_0_decoded_isStore (io_issue_0_decoded_isStore),
.io_issue_0_decoded_isBranch (io_issue_0_decoded_isBranch),
.io_issue_0_decoded_isJal (io_issue_0_decoded_isJal),
.io_issue_0_decoded_isJalr (io_issue_0_decoded_isJalr),
.io_issue_0_decoded_isLui (io_issue_0_decoded_isLui),
.io_issue_0_decoded_isAuipc (io_issue_0_decoded_isAuipc),
.io_issue_0_decoded_isOpImm (io_issue_0_decoded_isOpImm),
.io_issue_0_decoded_isWord (io_issue_0_decoded_isWord),
.io_issue_0_decoded_isSystem (io_issue_0_decoded_isSystem),
.io_issue_0_decoded_isFenceI (io_issue_0_decoded_isFenceI),
.io_issue_0_decoded_isAmo (io_issue_0_decoded_isAmo),
.io_issue_0_decoded_amoOp (io_issue_0_decoded_amoOp),
.io_issue_0_decoded_writesRd (io_issue_0_decoded_writesRd),
.io_issue_0_decoded_illegal (io_issue_0_decoded_illegal),
.io_issue_0_prs1 (io_issue_0_prs1),
.io_issue_0_prs2 (io_issue_0_prs2),
.io_issue_0_prd (io_issue_0_prd),
.io_issue_0_robIdx (io_issue_0_robIdx),
.io_issue_1_decoded_pc (io_issue_1_decoded_pc),
.io_issue_1_decoded_inst (io_issue_1_decoded_inst),
.io_issue_1_decoded_rs1 (io_issue_1_decoded_rs1),
.io_issue_1_decoded_funct3 (io_issue_1_decoded_funct3),
.io_issue_1_decoded_immI (io_issue_1_decoded_immI),
.io_issue_1_decoded_immS (io_issue_1_decoded_immS),
.io_issue_1_decoded_immB (io_issue_1_decoded_immB),
.io_issue_1_decoded_immU (io_issue_1_decoded_immU),
.io_issue_1_decoded_immJ (io_issue_1_decoded_immJ),
.io_issue_1_decoded_aluFn (io_issue_1_decoded_aluFn),
.io_issue_1_decoded_memWidth (io_issue_1_decoded_memWidth),
.io_issue_1_decoded_memSigned (io_issue_1_decoded_memSigned),
.io_issue_1_decoded_isLoad (io_issue_1_decoded_isLoad),
.io_issue_1_decoded_isStore (io_issue_1_decoded_isStore),
.io_issue_1_decoded_isBranch (io_issue_1_decoded_isBranch),
.io_issue_1_decoded_isJal (io_issue_1_decoded_isJal),
.io_issue_1_decoded_isJalr (io_issue_1_decoded_isJalr),
.io_issue_1_decoded_isLui (io_issue_1_decoded_isLui),
.io_issue_1_decoded_isAuipc (io_issue_1_decoded_isAuipc),
.io_issue_1_decoded_isOpImm (io_issue_1_decoded_isOpImm),
.io_issue_1_decoded_isWord (io_issue_1_decoded_isWord),
.io_issue_1_decoded_isSystem (io_issue_1_decoded_isSystem),
.io_issue_1_decoded_isFenceI (io_issue_1_decoded_isFenceI),
.io_issue_1_decoded_isAmo (io_issue_1_decoded_isAmo),
.io_issue_1_decoded_amoOp (io_issue_1_decoded_amoOp),
.io_issue_1_decoded_writesRd (io_issue_1_decoded_writesRd),
.io_issue_1_decoded_illegal (io_issue_1_decoded_illegal),
.io_issue_1_prs1 (io_issue_1_prs1),
.io_issue_1_prs2 (io_issue_1_prs2),
.io_issue_1_prd (io_issue_1_prd),
.io_issue_1_robIdx (io_issue_1_robIdx),
.io_issueReady_0 (io_issueReady_0),
.io_issueReady_1 (io_issueReady_1),
.io_flush (io_flush)
);
endmodule

306
generated-ooo/IssueStage.sv
View File

@@ -16,7 +16,8 @@ module IssueStage(
io_in_0_decoded_immJ,
input [4:0] io_in_0_decoded_aluFn,
input [2:0] io_in_0_decoded_memWidth,
input io_in_0_decoded_isLoad,
input io_in_0_decoded_memSigned,
io_in_0_decoded_isLoad,
io_in_0_decoded_isStore,
io_in_0_decoded_isBranch,
io_in_0_decoded_isJal,
@@ -26,7 +27,10 @@ module IssueStage(
io_in_0_decoded_isOpImm,
io_in_0_decoded_isWord,
io_in_0_decoded_isSystem,
io_in_0_decoded_writesRd,
io_in_0_decoded_isFenceI,
io_in_0_decoded_isAmo,
input [4:0] io_in_0_decoded_amoOp,
input io_in_0_decoded_writesRd,
io_in_0_decoded_illegal,
input [5:0] io_in_0_prs1,
io_in_0_prs2,
@@ -46,7 +50,8 @@ module IssueStage(
io_in_1_decoded_immJ,
input [4:0] io_in_1_decoded_aluFn,
input [2:0] io_in_1_decoded_memWidth,
input io_in_1_decoded_isLoad,
input io_in_1_decoded_memSigned,
io_in_1_decoded_isLoad,
io_in_1_decoded_isStore,
io_in_1_decoded_isBranch,
io_in_1_decoded_isJal,
@@ -56,7 +61,10 @@ module IssueStage(
io_in_1_decoded_isOpImm,
io_in_1_decoded_isWord,
io_in_1_decoded_isSystem,
io_in_1_decoded_writesRd,
io_in_1_decoded_isFenceI,
io_in_1_decoded_isAmo,
input [4:0] io_in_1_decoded_amoOp,
input io_in_1_decoded_writesRd,
io_in_1_decoded_illegal,
input [5:0] io_in_1_prs1,
io_in_1_prs2,
@@ -83,7 +91,8 @@ module IssueStage(
io_out_0_decoded_immJ,
output [4:0] io_out_0_decoded_aluFn,
output [2:0] io_out_0_decoded_memWidth,
output io_out_0_decoded_isLoad,
output io_out_0_decoded_memSigned,
io_out_0_decoded_isLoad,
io_out_0_decoded_isStore,
io_out_0_decoded_isBranch,
io_out_0_decoded_isJal,
@@ -93,7 +102,10 @@ module IssueStage(
io_out_0_decoded_isOpImm,
io_out_0_decoded_isWord,
io_out_0_decoded_isSystem,
io_out_0_decoded_writesRd,
io_out_0_decoded_isFenceI,
io_out_0_decoded_isAmo,
output [4:0] io_out_0_decoded_amoOp,
output io_out_0_decoded_writesRd,
io_out_0_decoded_illegal,
output [5:0] io_out_0_prs1,
io_out_0_prs2,
@@ -110,7 +122,8 @@ module IssueStage(
io_out_1_decoded_immJ,
output [4:0] io_out_1_decoded_aluFn,
output [2:0] io_out_1_decoded_memWidth,
output io_out_1_decoded_isLoad,
output io_out_1_decoded_memSigned,
io_out_1_decoded_isLoad,
io_out_1_decoded_isStore,
io_out_1_decoded_isBranch,
io_out_1_decoded_isJal,
@@ -120,7 +133,10 @@ module IssueStage(
io_out_1_decoded_isOpImm,
io_out_1_decoded_isWord,
io_out_1_decoded_isSystem,
io_out_1_decoded_writesRd,
io_out_1_decoded_isFenceI,
io_out_1_decoded_isAmo,
output [4:0] io_out_1_decoded_amoOp,
output io_out_1_decoded_writesRd,
io_out_1_decoded_illegal,
output [5:0] io_out_1_prs1,
io_out_1_prs2,
@@ -132,135 +148,151 @@ module IssueStage(
);
IssueQueue queue (
.clock (clock),
.reset (reset),
.io_enqValid_0 (io_inValid_0),
.io_enqValid_1 (io_inValid_1),
.io_enq_0_decoded_pc (io_in_0_decoded_pc),
.io_enq_0_decoded_inst (io_in_0_decoded_inst),
.io_enq_0_decoded_rs1 (io_in_0_decoded_rs1),
.io_enq_0_decoded_rs2 (io_in_0_decoded_rs2),
.io_enq_0_decoded_funct3 (io_in_0_decoded_funct3),
.io_enq_0_decoded_immI (io_in_0_decoded_immI),
.io_enq_0_decoded_immS (io_in_0_decoded_immS),
.io_enq_0_decoded_immB (io_in_0_decoded_immB),
.io_enq_0_decoded_immU (io_in_0_decoded_immU),
.io_enq_0_decoded_immJ (io_in_0_decoded_immJ),
.io_enq_0_decoded_aluFn (io_in_0_decoded_aluFn),
.io_enq_0_decoded_memWidth (io_in_0_decoded_memWidth),
.io_enq_0_decoded_isLoad (io_in_0_decoded_isLoad),
.io_enq_0_decoded_isStore (io_in_0_decoded_isStore),
.io_enq_0_decoded_isBranch (io_in_0_decoded_isBranch),
.io_enq_0_decoded_isJal (io_in_0_decoded_isJal),
.io_enq_0_decoded_isJalr (io_in_0_decoded_isJalr),
.io_enq_0_decoded_isLui (io_in_0_decoded_isLui),
.io_enq_0_decoded_isAuipc (io_in_0_decoded_isAuipc),
.io_enq_0_decoded_isOpImm (io_in_0_decoded_isOpImm),
.io_enq_0_decoded_isWord (io_in_0_decoded_isWord),
.io_enq_0_decoded_isSystem (io_in_0_decoded_isSystem),
.io_enq_0_decoded_writesRd (io_in_0_decoded_writesRd),
.io_enq_0_decoded_illegal (io_in_0_decoded_illegal),
.io_enq_0_prs1 (io_in_0_prs1),
.io_enq_0_prs2 (io_in_0_prs2),
.io_enq_0_src1Ready (io_in_0_src1Ready),
.io_enq_0_src2Ready (io_in_0_src2Ready),
.io_enq_0_prd (io_in_0_prd),
.io_enq_0_robIdx (io_in_0_robIdx),
.io_enq_1_decoded_pc (io_in_1_decoded_pc),
.io_enq_1_decoded_inst (io_in_1_decoded_inst),
.io_enq_1_decoded_rs1 (io_in_1_decoded_rs1),
.io_enq_1_decoded_rs2 (io_in_1_decoded_rs2),
.io_enq_1_decoded_funct3 (io_in_1_decoded_funct3),
.io_enq_1_decoded_immI (io_in_1_decoded_immI),
.io_enq_1_decoded_immS (io_in_1_decoded_immS),
.io_enq_1_decoded_immB (io_in_1_decoded_immB),
.io_enq_1_decoded_immU (io_in_1_decoded_immU),
.io_enq_1_decoded_immJ (io_in_1_decoded_immJ),
.io_enq_1_decoded_aluFn (io_in_1_decoded_aluFn),
.io_enq_1_decoded_memWidth (io_in_1_decoded_memWidth),
.io_enq_1_decoded_isLoad (io_in_1_decoded_isLoad),
.io_enq_1_decoded_isStore (io_in_1_decoded_isStore),
.io_enq_1_decoded_isBranch (io_in_1_decoded_isBranch),
.io_enq_1_decoded_isJal (io_in_1_decoded_isJal),
.io_enq_1_decoded_isJalr (io_in_1_decoded_isJalr),
.io_enq_1_decoded_isLui (io_in_1_decoded_isLui),
.io_enq_1_decoded_isAuipc (io_in_1_decoded_isAuipc),
.io_enq_1_decoded_isOpImm (io_in_1_decoded_isOpImm),
.io_enq_1_decoded_isWord (io_in_1_decoded_isWord),
.io_enq_1_decoded_isSystem (io_in_1_decoded_isSystem),
.io_enq_1_decoded_writesRd (io_in_1_decoded_writesRd),
.io_enq_1_decoded_illegal (io_in_1_decoded_illegal),
.io_enq_1_prs1 (io_in_1_prs1),
.io_enq_1_prs2 (io_in_1_prs2),
.io_enq_1_src1Ready (io_in_1_src1Ready),
.io_enq_1_src2Ready (io_in_1_src2Ready),
.io_enq_1_prd (io_in_1_prd),
.io_enq_1_robIdx (io_in_1_robIdx),
.io_enqReady_0 (io_inReady_0),
.io_enqReady_1 (io_inReady_1),
.io_wakeup_0_valid (io_wakeup_0_valid),
.io_wakeup_0_phys (io_wakeup_0_phys),
.io_wakeup_1_valid (io_wakeup_1_valid),
.io_wakeup_1_phys (io_wakeup_1_phys),
.io_issueValid_0 (io_outValid_0),
.io_issueValid_1 (io_outValid_1),
.io_issue_0_decoded_pc (io_out_0_decoded_pc),
.io_issue_0_decoded_inst (io_out_0_decoded_inst),
.io_issue_0_decoded_rs1 (io_out_0_decoded_rs1),
.io_issue_0_decoded_funct3 (io_out_0_decoded_funct3),
.io_issue_0_decoded_immI (io_out_0_decoded_immI),
.io_issue_0_decoded_immS (io_out_0_decoded_immS),
.io_issue_0_decoded_immB (io_out_0_decoded_immB),
.io_issue_0_decoded_immU (io_out_0_decoded_immU),
.io_issue_0_decoded_immJ (io_out_0_decoded_immJ),
.io_issue_0_decoded_aluFn (io_out_0_decoded_aluFn),
.io_issue_0_decoded_memWidth (io_out_0_decoded_memWidth),
.io_issue_0_decoded_isLoad (io_out_0_decoded_isLoad),
.io_issue_0_decoded_isStore (io_out_0_decoded_isStore),
.io_issue_0_decoded_isBranch (io_out_0_decoded_isBranch),
.io_issue_0_decoded_isJal (io_out_0_decoded_isJal),
.io_issue_0_decoded_isJalr (io_out_0_decoded_isJalr),
.io_issue_0_decoded_isLui (io_out_0_decoded_isLui),
.io_issue_0_decoded_isAuipc (io_out_0_decoded_isAuipc),
.io_issue_0_decoded_isOpImm (io_out_0_decoded_isOpImm),
.io_issue_0_decoded_isWord (io_out_0_decoded_isWord),
.io_issue_0_decoded_isSystem (io_out_0_decoded_isSystem),
.io_issue_0_decoded_writesRd (io_out_0_decoded_writesRd),
.io_issue_0_decoded_illegal (io_out_0_decoded_illegal),
.io_issue_0_prs1 (io_out_0_prs1),
.io_issue_0_prs2 (io_out_0_prs2),
.io_issue_0_prd (io_out_0_prd),
.io_issue_0_robIdx (io_out_0_robIdx),
.io_issue_1_decoded_pc (io_out_1_decoded_pc),
.io_issue_1_decoded_inst (io_out_1_decoded_inst),
.io_issue_1_decoded_rs1 (io_out_1_decoded_rs1),
.io_issue_1_decoded_funct3 (io_out_1_decoded_funct3),
.io_issue_1_decoded_immI (io_out_1_decoded_immI),
.io_issue_1_decoded_immS (io_out_1_decoded_immS),
.io_issue_1_decoded_immB (io_out_1_decoded_immB),
.io_issue_1_decoded_immU (io_out_1_decoded_immU),
.io_issue_1_decoded_immJ (io_out_1_decoded_immJ),
.io_issue_1_decoded_aluFn (io_out_1_decoded_aluFn),
.io_issue_1_decoded_memWidth (io_out_1_decoded_memWidth),
.io_issue_1_decoded_isLoad (io_out_1_decoded_isLoad),
.io_issue_1_decoded_isStore (io_out_1_decoded_isStore),
.io_issue_1_decoded_isBranch (io_out_1_decoded_isBranch),
.io_issue_1_decoded_isJal (io_out_1_decoded_isJal),
.io_issue_1_decoded_isJalr (io_out_1_decoded_isJalr),
.io_issue_1_decoded_isLui (io_out_1_decoded_isLui),
.io_issue_1_decoded_isAuipc (io_out_1_decoded_isAuipc),
.io_issue_1_decoded_isOpImm (io_out_1_decoded_isOpImm),
.io_issue_1_decoded_isWord (io_out_1_decoded_isWord),
.io_issue_1_decoded_isSystem (io_out_1_decoded_isSystem),
.io_issue_1_decoded_writesRd (io_out_1_decoded_writesRd),
.io_issue_1_decoded_illegal (io_out_1_decoded_illegal),
.io_issue_1_prs1 (io_out_1_prs1),
.io_issue_1_prs2 (io_out_1_prs2),
.io_issue_1_prd (io_out_1_prd),
.io_issue_1_robIdx (io_out_1_robIdx),
.io_issueReady_0 (io_outReady_0),
.io_issueReady_1 (io_outReady_1),
.io_flush (io_flush)
.clock (clock),
.reset (reset),
.io_enqValid_0 (io_inValid_0),
.io_enqValid_1 (io_inValid_1),
.io_enq_0_decoded_pc (io_in_0_decoded_pc),
.io_enq_0_decoded_inst (io_in_0_decoded_inst),
.io_enq_0_decoded_rs1 (io_in_0_decoded_rs1),
.io_enq_0_decoded_rs2 (io_in_0_decoded_rs2),
.io_enq_0_decoded_funct3 (io_in_0_decoded_funct3),
.io_enq_0_decoded_immI (io_in_0_decoded_immI),
.io_enq_0_decoded_immS (io_in_0_decoded_immS),
.io_enq_0_decoded_immB (io_in_0_decoded_immB),
.io_enq_0_decoded_immU (io_in_0_decoded_immU),
.io_enq_0_decoded_immJ (io_in_0_decoded_immJ),
.io_enq_0_decoded_aluFn (io_in_0_decoded_aluFn),
.io_enq_0_decoded_memWidth (io_in_0_decoded_memWidth),
.io_enq_0_decoded_memSigned (io_in_0_decoded_memSigned),
.io_enq_0_decoded_isLoad (io_in_0_decoded_isLoad),
.io_enq_0_decoded_isStore (io_in_0_decoded_isStore),
.io_enq_0_decoded_isBranch (io_in_0_decoded_isBranch),
.io_enq_0_decoded_isJal (io_in_0_decoded_isJal),
.io_enq_0_decoded_isJalr (io_in_0_decoded_isJalr),
.io_enq_0_decoded_isLui (io_in_0_decoded_isLui),
.io_enq_0_decoded_isAuipc (io_in_0_decoded_isAuipc),
.io_enq_0_decoded_isOpImm (io_in_0_decoded_isOpImm),
.io_enq_0_decoded_isWord (io_in_0_decoded_isWord),
.io_enq_0_decoded_isSystem (io_in_0_decoded_isSystem),
.io_enq_0_decoded_isFenceI (io_in_0_decoded_isFenceI),
.io_enq_0_decoded_isAmo (io_in_0_decoded_isAmo),
.io_enq_0_decoded_amoOp (io_in_0_decoded_amoOp),
.io_enq_0_decoded_writesRd (io_in_0_decoded_writesRd),
.io_enq_0_decoded_illegal (io_in_0_decoded_illegal),
.io_enq_0_prs1 (io_in_0_prs1),
.io_enq_0_prs2 (io_in_0_prs2),
.io_enq_0_src1Ready (io_in_0_src1Ready),
.io_enq_0_src2Ready (io_in_0_src2Ready),
.io_enq_0_prd (io_in_0_prd),
.io_enq_0_robIdx (io_in_0_robIdx),
.io_enq_1_decoded_pc (io_in_1_decoded_pc),
.io_enq_1_decoded_inst (io_in_1_decoded_inst),
.io_enq_1_decoded_rs1 (io_in_1_decoded_rs1),
.io_enq_1_decoded_rs2 (io_in_1_decoded_rs2),
.io_enq_1_decoded_funct3 (io_in_1_decoded_funct3),
.io_enq_1_decoded_immI (io_in_1_decoded_immI),
.io_enq_1_decoded_immS (io_in_1_decoded_immS),
.io_enq_1_decoded_immB (io_in_1_decoded_immB),
.io_enq_1_decoded_immU (io_in_1_decoded_immU),
.io_enq_1_decoded_immJ (io_in_1_decoded_immJ),
.io_enq_1_decoded_aluFn (io_in_1_decoded_aluFn),
.io_enq_1_decoded_memWidth (io_in_1_decoded_memWidth),
.io_enq_1_decoded_memSigned (io_in_1_decoded_memSigned),
.io_enq_1_decoded_isLoad (io_in_1_decoded_isLoad),
.io_enq_1_decoded_isStore (io_in_1_decoded_isStore),
.io_enq_1_decoded_isBranch (io_in_1_decoded_isBranch),
.io_enq_1_decoded_isJal (io_in_1_decoded_isJal),
.io_enq_1_decoded_isJalr (io_in_1_decoded_isJalr),
.io_enq_1_decoded_isLui (io_in_1_decoded_isLui),
.io_enq_1_decoded_isAuipc (io_in_1_decoded_isAuipc),
.io_enq_1_decoded_isOpImm (io_in_1_decoded_isOpImm),
.io_enq_1_decoded_isWord (io_in_1_decoded_isWord),
.io_enq_1_decoded_isSystem (io_in_1_decoded_isSystem),
.io_enq_1_decoded_isFenceI (io_in_1_decoded_isFenceI),
.io_enq_1_decoded_isAmo (io_in_1_decoded_isAmo),
.io_enq_1_decoded_amoOp (io_in_1_decoded_amoOp),
.io_enq_1_decoded_writesRd (io_in_1_decoded_writesRd),
.io_enq_1_decoded_illegal (io_in_1_decoded_illegal),
.io_enq_1_prs1 (io_in_1_prs1),
.io_enq_1_prs2 (io_in_1_prs2),
.io_enq_1_src1Ready (io_in_1_src1Ready),
.io_enq_1_src2Ready (io_in_1_src2Ready),
.io_enq_1_prd (io_in_1_prd),
.io_enq_1_robIdx (io_in_1_robIdx),
.io_enqReady_0 (io_inReady_0),
.io_enqReady_1 (io_inReady_1),
.io_wakeup_0_valid (io_wakeup_0_valid),
.io_wakeup_0_phys (io_wakeup_0_phys),
.io_wakeup_1_valid (io_wakeup_1_valid),
.io_wakeup_1_phys (io_wakeup_1_phys),
.io_issueValid_0 (io_outValid_0),
.io_issueValid_1 (io_outValid_1),
.io_issue_0_decoded_pc (io_out_0_decoded_pc),
.io_issue_0_decoded_inst (io_out_0_decoded_inst),
.io_issue_0_decoded_rs1 (io_out_0_decoded_rs1),
.io_issue_0_decoded_funct3 (io_out_0_decoded_funct3),
.io_issue_0_decoded_immI (io_out_0_decoded_immI),
.io_issue_0_decoded_immS (io_out_0_decoded_immS),
.io_issue_0_decoded_immB (io_out_0_decoded_immB),
.io_issue_0_decoded_immU (io_out_0_decoded_immU),
.io_issue_0_decoded_immJ (io_out_0_decoded_immJ),
.io_issue_0_decoded_aluFn (io_out_0_decoded_aluFn),
.io_issue_0_decoded_memWidth (io_out_0_decoded_memWidth),
.io_issue_0_decoded_memSigned (io_out_0_decoded_memSigned),
.io_issue_0_decoded_isLoad (io_out_0_decoded_isLoad),
.io_issue_0_decoded_isStore (io_out_0_decoded_isStore),
.io_issue_0_decoded_isBranch (io_out_0_decoded_isBranch),
.io_issue_0_decoded_isJal (io_out_0_decoded_isJal),
.io_issue_0_decoded_isJalr (io_out_0_decoded_isJalr),
.io_issue_0_decoded_isLui (io_out_0_decoded_isLui),
.io_issue_0_decoded_isAuipc (io_out_0_decoded_isAuipc),
.io_issue_0_decoded_isOpImm (io_out_0_decoded_isOpImm),
.io_issue_0_decoded_isWord (io_out_0_decoded_isWord),
.io_issue_0_decoded_isSystem (io_out_0_decoded_isSystem),
.io_issue_0_decoded_isFenceI (io_out_0_decoded_isFenceI),
.io_issue_0_decoded_isAmo (io_out_0_decoded_isAmo),
.io_issue_0_decoded_amoOp (io_out_0_decoded_amoOp),
.io_issue_0_decoded_writesRd (io_out_0_decoded_writesRd),
.io_issue_0_decoded_illegal (io_out_0_decoded_illegal),
.io_issue_0_prs1 (io_out_0_prs1),
.io_issue_0_prs2 (io_out_0_prs2),
.io_issue_0_prd (io_out_0_prd),
.io_issue_0_robIdx (io_out_0_robIdx),
.io_issue_1_decoded_pc (io_out_1_decoded_pc),
.io_issue_1_decoded_inst (io_out_1_decoded_inst),
.io_issue_1_decoded_rs1 (io_out_1_decoded_rs1),
.io_issue_1_decoded_funct3 (io_out_1_decoded_funct3),
.io_issue_1_decoded_immI (io_out_1_decoded_immI),
.io_issue_1_decoded_immS (io_out_1_decoded_immS),
.io_issue_1_decoded_immB (io_out_1_decoded_immB),
.io_issue_1_decoded_immU (io_out_1_decoded_immU),
.io_issue_1_decoded_immJ (io_out_1_decoded_immJ),
.io_issue_1_decoded_aluFn (io_out_1_decoded_aluFn),
.io_issue_1_decoded_memWidth (io_out_1_decoded_memWidth),
.io_issue_1_decoded_memSigned (io_out_1_decoded_memSigned),
.io_issue_1_decoded_isLoad (io_out_1_decoded_isLoad),
.io_issue_1_decoded_isStore (io_out_1_decoded_isStore),
.io_issue_1_decoded_isBranch (io_out_1_decoded_isBranch),
.io_issue_1_decoded_isJal (io_out_1_decoded_isJal),
.io_issue_1_decoded_isJalr (io_out_1_decoded_isJalr),
.io_issue_1_decoded_isLui (io_out_1_decoded_isLui),
.io_issue_1_decoded_isAuipc (io_out_1_decoded_isAuipc),
.io_issue_1_decoded_isOpImm (io_out_1_decoded_isOpImm),
.io_issue_1_decoded_isWord (io_out_1_decoded_isWord),
.io_issue_1_decoded_isSystem (io_out_1_decoded_isSystem),
.io_issue_1_decoded_isFenceI (io_out_1_decoded_isFenceI),
.io_issue_1_decoded_isAmo (io_out_1_decoded_isAmo),
.io_issue_1_decoded_amoOp (io_out_1_decoded_amoOp),
.io_issue_1_decoded_writesRd (io_out_1_decoded_writesRd),
.io_issue_1_decoded_illegal (io_out_1_decoded_illegal),
.io_issue_1_prs1 (io_out_1_prs1),
.io_issue_1_prs2 (io_out_1_prs2),
.io_issue_1_prd (io_out_1_prd),
.io_issue_1_robIdx (io_out_1_robIdx),
.io_issueReady_0 (io_outReady_0),
.io_issueReady_1 (io_outReady_1),
.io_flush (io_flush)
);
endmodule

6
generated-ooo/LSU.sv
View File

@@ -6,6 +6,9 @@ module LSU(
input [63:0] io_req_addr,
io_req_data,
input io_req_isStore,
io_req_isSigned,
io_req_isAmo,
input [4:0] io_req_amoOp,
input [2:0] io_req_size,
output io_reqReady,
input [63:0] io_satp,
@@ -88,6 +91,9 @@ module LSU(
.io_req_addr ((|(io_satp[63:60])) ? _dtlb_io_resp_paddr : io_req_addr),
.io_req_data (io_req_data),
.io_req_isStore (io_req_isStore),
.io_req_isSigned (io_req_isSigned),
.io_req_isAmo (io_req_isAmo),
.io_req_amoOp (io_req_amoOp),
.io_req_size (io_req_size),
.io_reqReady (_dcache_io_reqReady),
.io_memReqValid (_dcache_io_memReqValid),

148
generated-ooo/LoadQueue.sv
View File

@@ -11,6 +11,10 @@ module LoadQueue(
input [2:0] io_size,
input io_complete,
input [3:0] io_completeIdx,
input io_commitValid_0,
io_commitValid_1,
input [5:0] io_commitRobIdx_0,
io_commitRobIdx_1,
input io_storeAddrValid,
input [5:0] io_storeRobIdx,
input [63:0] io_storeAddr,
@@ -155,13 +159,30 @@ module LoadQueue(
|(_enqIdx_T_1[6:3]),
|(_enqIdx_T_3[2:1]),
_enqIdx_T_3[2] | _enqIdx_T_3[0]};
wire [5:0] _youngerLoad_diff_T = entries_0_robIdx - io_storeRobIdx;
wire _violationVec_15_bm_T = io_storeSize == 3'h0;
wire _violationVec_15_bm_T_2 = io_storeSize == 3'h1;
wire _violationVec_15_bm_T_4 = io_storeSize == 3'h2;
wire _violationVec_15_bm_T_6 = io_storeSize == 3'h3;
wire [5:0] _youngerLoad_diff_T_1 = entries_1_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_2 = entries_2_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_3 = entries_3_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_4 = entries_4_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_5 = entries_5_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_6 = entries_6_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_7 = entries_7_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_8 = entries_8_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_9 = entries_9_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_10 = entries_10_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_11 = entries_11_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_12 = entries_12_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_13 = entries_13_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_14 = entries_14_robIdx - io_storeRobIdx;
wire [5:0] _youngerLoad_diff_T_15 = entries_15_robIdx - io_storeRobIdx;
wire [15:0] _io_violation_T =
{io_storeAddrValid & entries_15_valid & entries_15_completed & entries_15_addrValid
& entries_15_robIdx > io_storeRobIdx & entries_15_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_15) & ~(_youngerLoad_diff_T_15[5])
& entries_15_addr[63:3] == io_storeAddr[63:3]
& (entries_15_addr[2:0]
| (entries_15_size == 3'h3
? 3'h7
@@ -179,7 +200,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_15_addr[2:0],
io_storeAddrValid & entries_14_valid & entries_14_completed & entries_14_addrValid
& entries_14_robIdx > io_storeRobIdx & entries_14_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_14) & ~(_youngerLoad_diff_T_14[5])
& entries_14_addr[63:3] == io_storeAddr[63:3]
& (entries_14_addr[2:0]
| (entries_14_size == 3'h3
? 3'h7
@@ -197,7 +219,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_14_addr[2:0],
io_storeAddrValid & entries_13_valid & entries_13_completed & entries_13_addrValid
& entries_13_robIdx > io_storeRobIdx & entries_13_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_13) & ~(_youngerLoad_diff_T_13[5])
& entries_13_addr[63:3] == io_storeAddr[63:3]
& (entries_13_addr[2:0]
| (entries_13_size == 3'h3
? 3'h7
@@ -215,7 +238,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_13_addr[2:0],
io_storeAddrValid & entries_12_valid & entries_12_completed & entries_12_addrValid
& entries_12_robIdx > io_storeRobIdx & entries_12_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_12) & ~(_youngerLoad_diff_T_12[5])
& entries_12_addr[63:3] == io_storeAddr[63:3]
& (entries_12_addr[2:0]
| (entries_12_size == 3'h3
? 3'h7
@@ -233,7 +257,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_12_addr[2:0],
io_storeAddrValid & entries_11_valid & entries_11_completed & entries_11_addrValid
& entries_11_robIdx > io_storeRobIdx & entries_11_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_11) & ~(_youngerLoad_diff_T_11[5])
& entries_11_addr[63:3] == io_storeAddr[63:3]
& (entries_11_addr[2:0]
| (entries_11_size == 3'h3
? 3'h7
@@ -251,7 +276,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_11_addr[2:0],
io_storeAddrValid & entries_10_valid & entries_10_completed & entries_10_addrValid
& entries_10_robIdx > io_storeRobIdx & entries_10_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_10) & ~(_youngerLoad_diff_T_10[5])
& entries_10_addr[63:3] == io_storeAddr[63:3]
& (entries_10_addr[2:0]
| (entries_10_size == 3'h3
? 3'h7
@@ -269,7 +295,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_10_addr[2:0],
io_storeAddrValid & entries_9_valid & entries_9_completed & entries_9_addrValid
& entries_9_robIdx > io_storeRobIdx & entries_9_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_9) & ~(_youngerLoad_diff_T_9[5])
& entries_9_addr[63:3] == io_storeAddr[63:3]
& (entries_9_addr[2:0]
| (entries_9_size == 3'h3
? 3'h7
@@ -287,7 +314,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_9_addr[2:0],
io_storeAddrValid & entries_8_valid & entries_8_completed & entries_8_addrValid
& entries_8_robIdx > io_storeRobIdx & entries_8_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_8) & ~(_youngerLoad_diff_T_8[5])
& entries_8_addr[63:3] == io_storeAddr[63:3]
& (entries_8_addr[2:0]
| (entries_8_size == 3'h3
? 3'h7
@@ -305,7 +333,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_8_addr[2:0],
io_storeAddrValid & entries_7_valid & entries_7_completed & entries_7_addrValid
& entries_7_robIdx > io_storeRobIdx & entries_7_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_7) & ~(_youngerLoad_diff_T_7[5])
& entries_7_addr[63:3] == io_storeAddr[63:3]
& (entries_7_addr[2:0]
| (entries_7_size == 3'h3
? 3'h7
@@ -323,7 +352,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_7_addr[2:0],
io_storeAddrValid & entries_6_valid & entries_6_completed & entries_6_addrValid
& entries_6_robIdx > io_storeRobIdx & entries_6_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_6) & ~(_youngerLoad_diff_T_6[5])
& entries_6_addr[63:3] == io_storeAddr[63:3]
& (entries_6_addr[2:0]
| (entries_6_size == 3'h3
? 3'h7
@@ -341,7 +371,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_6_addr[2:0],
io_storeAddrValid & entries_5_valid & entries_5_completed & entries_5_addrValid
& entries_5_robIdx > io_storeRobIdx & entries_5_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_5) & ~(_youngerLoad_diff_T_5[5])
& entries_5_addr[63:3] == io_storeAddr[63:3]
& (entries_5_addr[2:0]
| (entries_5_size == 3'h3
? 3'h7
@@ -359,7 +390,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_5_addr[2:0],
io_storeAddrValid & entries_4_valid & entries_4_completed & entries_4_addrValid
& entries_4_robIdx > io_storeRobIdx & entries_4_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_4) & ~(_youngerLoad_diff_T_4[5])
& entries_4_addr[63:3] == io_storeAddr[63:3]
& (entries_4_addr[2:0]
| (entries_4_size == 3'h3
? 3'h7
@@ -377,7 +409,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_4_addr[2:0],
io_storeAddrValid & entries_3_valid & entries_3_completed & entries_3_addrValid
& entries_3_robIdx > io_storeRobIdx & entries_3_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_3) & ~(_youngerLoad_diff_T_3[5])
& entries_3_addr[63:3] == io_storeAddr[63:3]
& (entries_3_addr[2:0]
| (entries_3_size == 3'h3
? 3'h7
@@ -395,7 +428,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_3_addr[2:0],
io_storeAddrValid & entries_2_valid & entries_2_completed & entries_2_addrValid
& entries_2_robIdx > io_storeRobIdx & entries_2_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_2) & ~(_youngerLoad_diff_T_2[5])
& entries_2_addr[63:3] == io_storeAddr[63:3]
& (entries_2_addr[2:0]
| (entries_2_size == 3'h3
? 3'h7
@@ -413,7 +447,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_2_addr[2:0],
io_storeAddrValid & entries_1_valid & entries_1_completed & entries_1_addrValid
& entries_1_robIdx > io_storeRobIdx & entries_1_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T_1) & ~(_youngerLoad_diff_T_1[5])
& entries_1_addr[63:3] == io_storeAddr[63:3]
& (entries_1_addr[2:0]
| (entries_1_size == 3'h3
? 3'h7
@@ -431,7 +466,8 @@ module LoadQueue(
? 3'h1
: _violationVec_15_bm_T ? 3'h0 : 3'h7)) >= entries_1_addr[2:0],
io_storeAddrValid & entries_0_valid & entries_0_completed & entries_0_addrValid
& entries_0_robIdx > io_storeRobIdx & entries_0_addr[63:3] == io_storeAddr[63:3]
& (|_youngerLoad_diff_T) & ~(_youngerLoad_diff_T[5])
& entries_0_addr[63:3] == io_storeAddr[63:3]
& (entries_0_addr[2:0]
| (entries_0_size == 3'h3
? 3'h7
@@ -630,7 +666,10 @@ module LoadQueue(
_GEN_29 = io_addrValid & io_addrIdx == 4'hD;
_GEN_30 = io_addrValid & io_addrIdx == 4'hE;
_GEN_31 = io_addrValid & (&io_addrIdx);
entries_0_valid <= ~io_flush & (_GEN_0 | entries_0_valid);
entries_0_valid <=
~(io_flush | io_commitValid_1 & entries_0_valid
& entries_0_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_0_valid
& entries_0_robIdx == io_commitRobIdx_0) & (_GEN_0 | entries_0_valid);
if (io_flush) begin
entries_0_robIdx <= 6'h0;
entries_0_addr <= 64'h0;
@@ -783,77 +822,122 @@ module LoadQueue(
entries_0_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h0 | ~_GEN_0 & entries_0_completed);
entries_1_valid <= ~io_flush & (_GEN_1 | entries_1_valid);
entries_1_valid <=
~(io_flush | io_commitValid_1 & entries_1_valid
& entries_1_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_1_valid
& entries_1_robIdx == io_commitRobIdx_0) & (_GEN_1 | entries_1_valid);
entries_1_addrValid <= ~io_flush & (_GEN_17 | ~_GEN_1 & entries_1_addrValid);
entries_1_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h1 | ~_GEN_1 & entries_1_completed);
entries_2_valid <= ~io_flush & (_GEN_2 | entries_2_valid);
entries_2_valid <=
~(io_flush | io_commitValid_1 & entries_2_valid
& entries_2_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_2_valid
& entries_2_robIdx == io_commitRobIdx_0) & (_GEN_2 | entries_2_valid);
entries_2_addrValid <= ~io_flush & (_GEN_18 | ~_GEN_2 & entries_2_addrValid);
entries_2_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h2 | ~_GEN_2 & entries_2_completed);
entries_3_valid <= ~io_flush & (_GEN_3 | entries_3_valid);
entries_3_valid <=
~(io_flush | io_commitValid_1 & entries_3_valid
& entries_3_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_3_valid
& entries_3_robIdx == io_commitRobIdx_0) & (_GEN_3 | entries_3_valid);
entries_3_addrValid <= ~io_flush & (_GEN_19 | ~_GEN_3 & entries_3_addrValid);
entries_3_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h3 | ~_GEN_3 & entries_3_completed);
entries_4_valid <= ~io_flush & (_GEN_4 | entries_4_valid);
entries_4_valid <=
~(io_flush | io_commitValid_1 & entries_4_valid
& entries_4_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_4_valid
& entries_4_robIdx == io_commitRobIdx_0) & (_GEN_4 | entries_4_valid);
entries_4_addrValid <= ~io_flush & (_GEN_20 | ~_GEN_4 & entries_4_addrValid);
entries_4_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h4 | ~_GEN_4 & entries_4_completed);
entries_5_valid <= ~io_flush & (_GEN_5 | entries_5_valid);
entries_5_valid <=
~(io_flush | io_commitValid_1 & entries_5_valid
& entries_5_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_5_valid
& entries_5_robIdx == io_commitRobIdx_0) & (_GEN_5 | entries_5_valid);
entries_5_addrValid <= ~io_flush & (_GEN_21 | ~_GEN_5 & entries_5_addrValid);
entries_5_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h5 | ~_GEN_5 & entries_5_completed);
entries_6_valid <= ~io_flush & (_GEN_6 | entries_6_valid);
entries_6_valid <=
~(io_flush | io_commitValid_1 & entries_6_valid
& entries_6_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_6_valid
& entries_6_robIdx == io_commitRobIdx_0) & (_GEN_6 | entries_6_valid);
entries_6_addrValid <= ~io_flush & (_GEN_22 | ~_GEN_6 & entries_6_addrValid);
entries_6_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h6 | ~_GEN_6 & entries_6_completed);
entries_7_valid <= ~io_flush & (_GEN_7 | entries_7_valid);
entries_7_valid <=
~(io_flush | io_commitValid_1 & entries_7_valid
& entries_7_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_7_valid
& entries_7_robIdx == io_commitRobIdx_0) & (_GEN_7 | entries_7_valid);
entries_7_addrValid <= ~io_flush & (_GEN_23 | ~_GEN_7 & entries_7_addrValid);
entries_7_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h7 | ~_GEN_7 & entries_7_completed);
entries_8_valid <= ~io_flush & (_GEN_8 | entries_8_valid);
entries_8_valid <=
~(io_flush | io_commitValid_1 & entries_8_valid
& entries_8_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_8_valid
& entries_8_robIdx == io_commitRobIdx_0) & (_GEN_8 | entries_8_valid);
entries_8_addrValid <= ~io_flush & (_GEN_24 | ~_GEN_8 & entries_8_addrValid);
entries_8_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h8 | ~_GEN_8 & entries_8_completed);
entries_9_valid <= ~io_flush & (_GEN_9 | entries_9_valid);
entries_9_valid <=
~(io_flush | io_commitValid_1 & entries_9_valid
& entries_9_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_9_valid
& entries_9_robIdx == io_commitRobIdx_0) & (_GEN_9 | entries_9_valid);
entries_9_addrValid <= ~io_flush & (_GEN_25 | ~_GEN_9 & entries_9_addrValid);
entries_9_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'h9 | ~_GEN_9 & entries_9_completed);
entries_10_valid <= ~io_flush & (_GEN_10 | entries_10_valid);
entries_10_valid <=
~(io_flush | io_commitValid_1 & entries_10_valid
& entries_10_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_10_valid
& entries_10_robIdx == io_commitRobIdx_0) & (_GEN_10 | entries_10_valid);
entries_10_addrValid <= ~io_flush & (_GEN_26 | ~_GEN_10 & entries_10_addrValid);
entries_10_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'hA | ~_GEN_10 & entries_10_completed);
entries_11_valid <= ~io_flush & (_GEN_11 | entries_11_valid);
entries_11_valid <=
~(io_flush | io_commitValid_1 & entries_11_valid
& entries_11_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_11_valid
& entries_11_robIdx == io_commitRobIdx_0) & (_GEN_11 | entries_11_valid);
entries_11_addrValid <= ~io_flush & (_GEN_27 | ~_GEN_11 & entries_11_addrValid);
entries_11_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'hB | ~_GEN_11 & entries_11_completed);
entries_12_valid <= ~io_flush & (_GEN_12 | entries_12_valid);
entries_12_valid <=
~(io_flush | io_commitValid_1 & entries_12_valid
& entries_12_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_12_valid
& entries_12_robIdx == io_commitRobIdx_0) & (_GEN_12 | entries_12_valid);
entries_12_addrValid <= ~io_flush & (_GEN_28 | ~_GEN_12 & entries_12_addrValid);
entries_12_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'hC | ~_GEN_12 & entries_12_completed);
entries_13_valid <= ~io_flush & (_GEN_13 | entries_13_valid);
entries_13_valid <=
~(io_flush | io_commitValid_1 & entries_13_valid
& entries_13_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_13_valid
& entries_13_robIdx == io_commitRobIdx_0) & (_GEN_13 | entries_13_valid);
entries_13_addrValid <= ~io_flush & (_GEN_29 | ~_GEN_13 & entries_13_addrValid);
entries_13_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'hD | ~_GEN_13 & entries_13_completed);
entries_14_valid <= ~io_flush & (_GEN_14 | entries_14_valid);
entries_14_valid <=
~(io_flush | io_commitValid_1 & entries_14_valid
& entries_14_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_14_valid
& entries_14_robIdx == io_commitRobIdx_0) & (_GEN_14 | entries_14_valid);
entries_14_addrValid <= ~io_flush & (_GEN_30 | ~_GEN_14 & entries_14_addrValid);
entries_14_completed <=
~io_flush
& (io_complete & io_completeIdx == 4'hE | ~_GEN_14 & entries_14_completed);
entries_15_valid <= ~io_flush & (_GEN_15 | entries_15_valid);
entries_15_valid <=
~(io_flush | io_commitValid_1 & entries_15_valid
& entries_15_robIdx == io_commitRobIdx_1 | io_commitValid_0 & entries_15_valid
& entries_15_robIdx == io_commitRobIdx_0) & (_GEN_15 | entries_15_valid);
entries_15_addrValid <= ~io_flush & (_GEN_31 | ~_GEN_15 & entries_15_addrValid);
entries_15_completed <=
~io_flush & (io_complete & (&io_completeIdx) | ~_GEN_15 & entries_15_completed);

520
generated-ooo/OoOBackend.sv
View File

@@ -18,7 +18,8 @@ module OoOBackend(
input [3:0] io_decode_0_opClass,
input [4:0] io_decode_0_aluFn,
input [2:0] io_decode_0_memWidth,
input io_decode_0_isLoad,
input io_decode_0_memSigned,
io_decode_0_isLoad,
io_decode_0_isStore,
io_decode_0_isBranch,
io_decode_0_isJal,
@@ -28,7 +29,10 @@ module OoOBackend(
io_decode_0_isOpImm,
io_decode_0_isWord,
io_decode_0_isSystem,
io_decode_0_writesRd,
io_decode_0_isFenceI,
io_decode_0_isAmo,
input [4:0] io_decode_0_amoOp,
input io_decode_0_writesRd,
io_decode_0_illegal,
input [63:0] io_decode_1_pc,
input [31:0] io_decode_1_inst,
@@ -44,7 +48,8 @@ module OoOBackend(
input [3:0] io_decode_1_opClass,
input [4:0] io_decode_1_aluFn,
input [2:0] io_decode_1_memWidth,
input io_decode_1_isLoad,
input io_decode_1_memSigned,
io_decode_1_isLoad,
io_decode_1_isStore,
io_decode_1_isBranch,
io_decode_1_isJal,
@@ -54,12 +59,16 @@ module OoOBackend(
io_decode_1_isOpImm,
io_decode_1_isWord,
io_decode_1_isSystem,
io_decode_1_writesRd,
io_decode_1_isFenceI,
io_decode_1_isAmo,
input [4:0] io_decode_1_amoOp,
input io_decode_1_writesRd,
io_decode_1_illegal,
output io_decodeReady,
io_flush,
output [63:0] io_redirectPc,
output io_dmemReqValid,
output io_invalidateICache,
io_dmemReqValid,
output [63:0] io_dmemReq_addr,
io_dmemReq_data,
output io_dmemReq_isStore,
@@ -78,6 +87,9 @@ module OoOBackend(
wire _lsu_io_pageFault;
wire [3:0] _sq_io_enqIdx;
wire _sq_io_forwardValid;
wire [63:0] _sq_io_forwardData;
wire _sq_io_forwardBlock;
wire _sq_io_olderStoreValid;
wire _sq_io_drainValid;
wire [63:0] _sq_io_drain_addr;
wire [63:0] _sq_io_drain_data;
@@ -132,6 +144,7 @@ module OoOBackend(
wire [63:0] _issue_io_out_0_decoded_immJ;
wire [4:0] _issue_io_out_0_decoded_aluFn;
wire [2:0] _issue_io_out_0_decoded_memWidth;
wire _issue_io_out_0_decoded_memSigned;
wire _issue_io_out_0_decoded_isLoad;
wire _issue_io_out_0_decoded_isStore;
wire _issue_io_out_0_decoded_isBranch;
@@ -142,6 +155,9 @@ module OoOBackend(
wire _issue_io_out_0_decoded_isOpImm;
wire _issue_io_out_0_decoded_isWord;
wire _issue_io_out_0_decoded_isSystem;
wire _issue_io_out_0_decoded_isFenceI;
wire _issue_io_out_0_decoded_isAmo;
wire [4:0] _issue_io_out_0_decoded_amoOp;
wire _issue_io_out_0_decoded_writesRd;
wire _issue_io_out_0_decoded_illegal;
wire [5:0] _issue_io_out_0_prs1;
@@ -159,6 +175,7 @@ module OoOBackend(
wire [63:0] _issue_io_out_1_decoded_immJ;
wire [4:0] _issue_io_out_1_decoded_aluFn;
wire [2:0] _issue_io_out_1_decoded_memWidth;
wire _issue_io_out_1_decoded_memSigned;
wire _issue_io_out_1_decoded_isLoad;
wire _issue_io_out_1_decoded_isStore;
wire _issue_io_out_1_decoded_isBranch;
@@ -169,6 +186,9 @@ module OoOBackend(
wire _issue_io_out_1_decoded_isOpImm;
wire _issue_io_out_1_decoded_isWord;
wire _issue_io_out_1_decoded_isSystem;
wire _issue_io_out_1_decoded_isFenceI;
wire _issue_io_out_1_decoded_isAmo;
wire [4:0] _issue_io_out_1_decoded_amoOp;
wire _issue_io_out_1_decoded_writesRd;
wire _issue_io_out_1_decoded_illegal;
wire [5:0] _issue_io_out_1_prs1;
@@ -189,6 +209,7 @@ module OoOBackend(
wire [63:0] _rename_io_out_0_decoded_immJ;
wire [4:0] _rename_io_out_0_decoded_aluFn;
wire [2:0] _rename_io_out_0_decoded_memWidth;
wire _rename_io_out_0_decoded_memSigned;
wire _rename_io_out_0_decoded_isLoad;
wire _rename_io_out_0_decoded_isStore;
wire _rename_io_out_0_decoded_isBranch;
@@ -199,6 +220,9 @@ module OoOBackend(
wire _rename_io_out_0_decoded_isOpImm;
wire _rename_io_out_0_decoded_isWord;
wire _rename_io_out_0_decoded_isSystem;
wire _rename_io_out_0_decoded_isFenceI;
wire _rename_io_out_0_decoded_isAmo;
wire [4:0] _rename_io_out_0_decoded_amoOp;
wire _rename_io_out_0_decoded_writesRd;
wire _rename_io_out_0_decoded_illegal;
wire [5:0] _rename_io_out_0_prs1;
@@ -219,6 +243,7 @@ module OoOBackend(
wire [63:0] _rename_io_out_1_decoded_immJ;
wire [4:0] _rename_io_out_1_decoded_aluFn;
wire [2:0] _rename_io_out_1_decoded_memWidth;
wire _rename_io_out_1_decoded_memSigned;
wire _rename_io_out_1_decoded_isLoad;
wire _rename_io_out_1_decoded_isStore;
wire _rename_io_out_1_decoded_isBranch;
@@ -229,6 +254,9 @@ module OoOBackend(
wire _rename_io_out_1_decoded_isOpImm;
wire _rename_io_out_1_decoded_isWord;
wire _rename_io_out_1_decoded_isSystem;
wire _rename_io_out_1_decoded_isFenceI;
wire _rename_io_out_1_decoded_isAmo;
wire [4:0] _rename_io_out_1_decoded_amoOp;
wire _rename_io_out_1_decoded_writesRd;
wire _rename_io_out_1_decoded_illegal;
wire [5:0] _rename_io_out_1_prs1;
@@ -256,6 +284,7 @@ module OoOBackend(
wire [2:0] _rename_io_commitEntry_0_csrCmd;
wire [63:0] _rename_io_commitEntry_0_csrRs1;
wire [4:0] _rename_io_commitEntry_0_csrZimm;
wire _rename_io_commitEntry_0_fenceI;
wire [5:0] _rename_io_commitEntry_1_robIdx;
wire [4:0] _rename_io_commitEntry_1_archDest;
wire _rename_io_commitEntry_1_writesDest;
@@ -272,6 +301,7 @@ module OoOBackend(
wire [2:0] _rename_io_commitEntry_1_csrCmd;
wire [63:0] _rename_io_commitEntry_1_csrRs1;
wire [4:0] _rename_io_commitEntry_1_csrZimm;
wire _rename_io_commitEntry_1_fenceI;
reg wakeupReg_0_valid;
reg [5:0] wakeupReg_0_phys;
reg wakeupReg_1_valid;
@@ -280,87 +310,135 @@ module OoOBackend(
reg [5:0] loadPendingRob;
reg [5:0] loadPendingPhys;
reg [3:0] loadPendingLq;
wire loadRespValid = _lsu_io_respValid & loadPending;
reg forwardPending;
reg [5:0] forwardPendingRob;
reg [5:0] forwardPendingPhys;
reg [3:0] forwardPendingLq;
reg [63:0] forwardPendingData;
wire loadRespValid = _lsu_io_respValid & loadPending | forwardPending;
wire isMem0 = _issue_io_out_0_decoded_isLoad | _issue_io_out_0_decoded_isStore;
wire memIssue_0 = _issue_io_outValid_0 & isMem0;
wire isMem1 = _issue_io_out_1_decoded_isLoad | _issue_io_out_1_decoded_isStore;
wire csrReadReq_0 =
_issue_io_outValid_0 & _issue_io_out_0_decoded_isSystem
& (|_issue_io_out_0_decoded_funct3);
wire _memReady1_T_1 = _lsu_io_reqReady & ~loadPending;
wire issue_io_outReady_0 = ~isMem0 | _memReady1_T_1;
wire _amoBlocked1_T = _sq_io_olderStoreValid | _sq_io_drainValid;
wire _memReady1_T_1 = _lsu_io_reqReady & ~loadPending & ~forwardPending;
wire issue_io_outReady_0 =
(~isMem0 | _memReady1_T_1 & ~(_issue_io_out_0_decoded_isAmo & _amoBlocked1_T)
& ~(_issue_io_out_0_decoded_isLoad & _sq_io_forwardBlock)) & ~loadPending
& ~forwardPending;
wire issue_io_outReady_1 =
(~isMem1 | _memReady1_T_1 & ~memIssue_0)
(~isMem1 | _memReady1_T_1 & ~memIssue_0
& ~(_issue_io_out_1_decoded_isAmo & _amoBlocked1_T)
& ~(_issue_io_out_1_decoded_isLoad & _sq_io_forwardBlock))
& ~(csrReadReq_0 & _issue_io_outValid_1 & _issue_io_out_1_decoded_isSystem
& (|_issue_io_out_1_decoded_funct3));
wire issueFire_0 = _issue_io_outValid_0 & issue_io_outReady_0;
wire issueFire_1 = _issue_io_outValid_1 & issue_io_outReady_1;
wire [63:0] memSrc2 = memIssue_0 ? _prf_io_rdata_1 : _prf_io_rdata_3;
wire [2:0] sq_io_size =
memIssue_0 ? _issue_io_out_0_decoded_memWidth : _issue_io_out_1_decoded_memWidth;
wire _GEN =
memIssue_0 ? _issue_io_out_0_decoded_memSigned : _issue_io_out_1_decoded_memSigned;
wire _GEN_0 =
memIssue_0 ? _issue_io_out_0_decoded_isStore : _issue_io_out_1_decoded_isStore;
wire loadReq_isAmo =
memIssue_0 ? _issue_io_out_0_decoded_isAmo : _issue_io_out_1_decoded_isAmo;
wire [5:0] sq_io_enqRobIdx =
memIssue_0 ? _issue_io_out_0_robIdx : _issue_io_out_1_robIdx;
wire [63:0] _memAddr_T_1 =
wire [63:0] _memAddr_T_2 =
(memIssue_0 ? _prf_io_rdata_0 : _prf_io_rdata_2)
+ (_GEN
? (memIssue_0 ? _issue_io_out_0_decoded_immS : _issue_io_out_1_decoded_immS)
: memIssue_0 ? _issue_io_out_0_decoded_immI : _issue_io_out_1_decoded_immI);
+ (loadReq_isAmo
? 64'h0
: _GEN_0
? (memIssue_0 ? _issue_io_out_0_decoded_immS : _issue_io_out_1_decoded_immS)
: memIssue_0 ? _issue_io_out_0_decoded_immI : _issue_io_out_1_decoded_immI);
wire _storeEnq_T = memIssue_0 | ~memIssue_0 & _issue_io_outValid_1 & isMem1;
wire _GEN_0 = memIssue_0 ? issue_io_outReady_0 : issue_io_outReady_1;
wire _GEN_1 = memIssue_0 ? issue_io_outReady_0 : issue_io_outReady_1;
wire loadEnq =
_storeEnq_T
& (memIssue_0 ? _issue_io_out_0_decoded_isLoad : _issue_io_out_1_decoded_isLoad)
& _GEN_0;
wire storeEnq = _storeEnq_T & _GEN & _GEN_0;
wire lsuLoadReq = loadEnq & ~_sq_io_forwardValid;
& _GEN_1;
wire storeEnq = _storeEnq_T & _GEN_0 & _GEN_1;
wire sqForwardValid = _sq_io_forwardValid & ~loadReq_isAmo;
wire lsuLoadReq = loadEnq & ~sqForwardValid;
wire _commitCsr0_T = _commit_io_commitReady_0 & _rename_io_commitValid_0;
wire commitStore0 = _commitCsr0_T & _rename_io_commitEntry_0_opClass == 4'h4;
wire _commitCsr1_T = _commit_io_commitReady_1 & _rename_io_commitValid_1;
wire commitStore0 = _commitCsr0_T & _rename_io_commitEntry_0_opClass == 4'h4;
wire commitCsr0 = _commitCsr0_T & _rename_io_commitEntry_0_csrValid;
wire _completeMispredict_0_T =
_issue_io_out_0_decoded_isJal | _issue_io_out_0_decoded_isJalr;
wire [63:0] _branchRedirect_T_1 = _issue_io_out_0_decoded_pc + 64'h4;
wire [63:0] _jalrTarget_T = _prf_io_rdata_0 + _issue_io_out_0_decoded_immI;
wire _completeMispredict_0_T_2 =
wire _completeMispredict_0_T_3 =
_issue_io_out_0_decoded_isBranch & _exec_0_io_branchTaken;
wire isEcall = _issue_io_out_0_decoded_inst == 32'h73;
wire isEbreak = _issue_io_out_0_decoded_inst == 32'h100073;
wire isMret = _issue_io_out_0_decoded_inst == 32'h30200073;
wire _completeCause_0_T = loadRespValid & _lsu_io_pageFault;
wire _completeCause_0_T = loadRespValid & ~forwardPending & _lsu_io_pageFault;
wire _completeMispredict_1_T =
_issue_io_out_1_decoded_isJal | _issue_io_out_1_decoded_isJalr;
wire [63:0] _branchRedirect_T_6 = _issue_io_out_1_decoded_pc + 64'h4;
wire [63:0] _jalrTarget_T_3 = _prf_io_rdata_2 + _issue_io_out_1_decoded_immI;
wire _completeMispredict_1_T_2 =
wire _completeMispredict_1_T_3 =
_issue_io_out_1_decoded_isBranch & _exec_1_io_branchTaken;
wire isEcall_1 = _issue_io_out_1_decoded_inst == 32'h73;
wire isEbreak_1 = _issue_io_out_1_decoded_inst == 32'h100073;
wire isMret_1 = _issue_io_out_1_decoded_inst == 32'h30200073;
always @(posedge clock) begin
automatic logic _GEN_1;
_GEN_1 = loadEnq & ~_sq_io_forwardValid;
automatic logic [5:0] _GEN_2;
automatic logic forwardLoad;
automatic logic _GEN_3;
automatic logic _GEN_4;
_GEN_2 = memIssue_0 ? _issue_io_out_0_prd : _issue_io_out_1_prd;
forwardLoad = loadEnq & sqForwardValid;
_GEN_3 = loadEnq & ~sqForwardValid;
_GEN_4 = forwardLoad | forwardPending;
if (reset) begin
wakeupReg_0_valid <= 1'h0;
wakeupReg_0_phys <= 6'h0;
wakeupReg_1_valid <= 1'h0;
wakeupReg_1_phys <= 6'h0;
loadPending <= 1'h0;
forwardPending <= 1'h0;
end
else begin
wakeupReg_0_valid <= _wb_0_io_wen;
wakeupReg_0_phys <= _wb_0_io_waddr;
wakeupReg_1_valid <= _wb_1_io_wen;
wakeupReg_1_phys <= _wb_1_io_waddr;
loadPending <= ~_commit_io_flush & (_GEN_1 | ~loadRespValid & loadPending);
loadPending <=
~_commit_io_flush
& (_GEN_4 ? loadPending : _GEN_3 | ~loadRespValid & loadPending);
forwardPending <= ~_commit_io_flush & forwardLoad;
end
if (_commit_io_flush | ~_GEN_1) begin
if (_commit_io_flush | _GEN_4 | ~_GEN_3) begin
end
else begin
loadPendingRob <= sq_io_enqRobIdx;
loadPendingPhys <= memIssue_0 ? _issue_io_out_0_prd : _issue_io_out_1_prd;
loadPendingPhys <= _GEN_2;
loadPendingLq <= _lq_io_enqIdx;
end
if (_commit_io_flush | ~forwardLoad) begin
end
else begin
forwardPendingRob <= sq_io_enqRobIdx;
forwardPendingPhys <= _GEN_2;
forwardPendingLq <= _lq_io_enqIdx;
forwardPendingData <=
sq_io_size == 3'h3
? _sq_io_forwardData
: sq_io_size == 3'h2
? {_GEN ? {32{_sq_io_forwardData[31]}} : 32'h0, _sq_io_forwardData[31:0]}
: sq_io_size == 3'h1
? {_GEN ? {48{_sq_io_forwardData[15]}} : 48'h0,
_sq_io_forwardData[15:0]}
: sq_io_size == 3'h0
? {_GEN ? {56{_sq_io_forwardData[7]}} : 56'h0,
_sq_io_forwardData[7:0]}
: _sq_io_forwardData;
end
end // always @(posedge)
RenameStage rename (
.clock (clock),
@@ -381,6 +459,7 @@ module OoOBackend(
.io_in_0_opClass (io_decode_0_opClass),
.io_in_0_aluFn (io_decode_0_aluFn),
.io_in_0_memWidth (io_decode_0_memWidth),
.io_in_0_memSigned (io_decode_0_memSigned),
.io_in_0_isLoad (io_decode_0_isLoad),
.io_in_0_isStore (io_decode_0_isStore),
.io_in_0_isBranch (io_decode_0_isBranch),
@@ -391,6 +470,9 @@ module OoOBackend(
.io_in_0_isOpImm (io_decode_0_isOpImm),
.io_in_0_isWord (io_decode_0_isWord),
.io_in_0_isSystem (io_decode_0_isSystem),
.io_in_0_isFenceI (io_decode_0_isFenceI),
.io_in_0_isAmo (io_decode_0_isAmo),
.io_in_0_amoOp (io_decode_0_amoOp),
.io_in_0_writesRd (io_decode_0_writesRd),
.io_in_0_illegal (io_decode_0_illegal),
.io_in_1_pc (io_decode_1_pc),
@@ -407,6 +489,7 @@ module OoOBackend(
.io_in_1_opClass (io_decode_1_opClass),
.io_in_1_aluFn (io_decode_1_aluFn),
.io_in_1_memWidth (io_decode_1_memWidth),
.io_in_1_memSigned (io_decode_1_memSigned),
.io_in_1_isLoad (io_decode_1_isLoad),
.io_in_1_isStore (io_decode_1_isStore),
.io_in_1_isBranch (io_decode_1_isBranch),
@@ -417,6 +500,9 @@ module OoOBackend(
.io_in_1_isOpImm (io_decode_1_isOpImm),
.io_in_1_isWord (io_decode_1_isWord),
.io_in_1_isSystem (io_decode_1_isSystem),
.io_in_1_isFenceI (io_decode_1_isFenceI),
.io_in_1_isAmo (io_decode_1_isAmo),
.io_in_1_amoOp (io_decode_1_amoOp),
.io_in_1_writesRd (io_decode_1_writesRd),
.io_in_1_illegal (io_decode_1_illegal),
.io_outValid_0 (_rename_io_outValid_0),
@@ -433,6 +519,7 @@ module OoOBackend(
.io_out_0_decoded_immJ (_rename_io_out_0_decoded_immJ),
.io_out_0_decoded_aluFn (_rename_io_out_0_decoded_aluFn),
.io_out_0_decoded_memWidth (_rename_io_out_0_decoded_memWidth),
.io_out_0_decoded_memSigned (_rename_io_out_0_decoded_memSigned),
.io_out_0_decoded_isLoad (_rename_io_out_0_decoded_isLoad),
.io_out_0_decoded_isStore (_rename_io_out_0_decoded_isStore),
.io_out_0_decoded_isBranch (_rename_io_out_0_decoded_isBranch),
@@ -443,6 +530,9 @@ module OoOBackend(
.io_out_0_decoded_isOpImm (_rename_io_out_0_decoded_isOpImm),
.io_out_0_decoded_isWord (_rename_io_out_0_decoded_isWord),
.io_out_0_decoded_isSystem (_rename_io_out_0_decoded_isSystem),
.io_out_0_decoded_isFenceI (_rename_io_out_0_decoded_isFenceI),
.io_out_0_decoded_isAmo (_rename_io_out_0_decoded_isAmo),
.io_out_0_decoded_amoOp (_rename_io_out_0_decoded_amoOp),
.io_out_0_decoded_writesRd (_rename_io_out_0_decoded_writesRd),
.io_out_0_decoded_illegal (_rename_io_out_0_decoded_illegal),
.io_out_0_prs1 (_rename_io_out_0_prs1),
@@ -463,6 +553,7 @@ module OoOBackend(
.io_out_1_decoded_immJ (_rename_io_out_1_decoded_immJ),
.io_out_1_decoded_aluFn (_rename_io_out_1_decoded_aluFn),
.io_out_1_decoded_memWidth (_rename_io_out_1_decoded_memWidth),
.io_out_1_decoded_memSigned (_rename_io_out_1_decoded_memSigned),
.io_out_1_decoded_isLoad (_rename_io_out_1_decoded_isLoad),
.io_out_1_decoded_isStore (_rename_io_out_1_decoded_isStore),
.io_out_1_decoded_isBranch (_rename_io_out_1_decoded_isBranch),
@@ -473,6 +564,9 @@ module OoOBackend(
.io_out_1_decoded_isOpImm (_rename_io_out_1_decoded_isOpImm),
.io_out_1_decoded_isWord (_rename_io_out_1_decoded_isWord),
.io_out_1_decoded_isSystem (_rename_io_out_1_decoded_isSystem),
.io_out_1_decoded_isFenceI (_rename_io_out_1_decoded_isFenceI),
.io_out_1_decoded_isAmo (_rename_io_out_1_decoded_isAmo),
.io_out_1_decoded_amoOp (_rename_io_out_1_decoded_amoOp),
.io_out_1_decoded_writesRd (_rename_io_out_1_decoded_writesRd),
.io_out_1_decoded_illegal (_rename_io_out_1_decoded_illegal),
.io_out_1_prs1 (_rename_io_out_1_prs1),
@@ -490,7 +584,9 @@ module OoOBackend(
(issueFire_0 & ~_issue_io_out_0_decoded_isLoad | loadRespValid),
.io_completeValid_1 (issueFire_1 & ~_issue_io_out_1_decoded_isLoad),
.io_completeIdx_0
(loadRespValid ? loadPendingRob : _issue_io_out_0_robIdx),
(loadRespValid
? (forwardPending ? forwardPendingRob : loadPendingRob)
: _issue_io_out_0_robIdx),
.io_completeIdx_1 (_issue_io_out_1_robIdx),
.io_completeException_0
(issueFire_0
@@ -518,9 +614,13 @@ module OoOBackend(
.io_completeBadAddr_0 (_issue_io_out_0_decoded_pc),
.io_completeBadAddr_1 (_issue_io_out_1_decoded_pc),
.io_completeMispredict_0
(issueFire_0 & (_completeMispredict_0_T | isMret | _completeMispredict_0_T_2)),
(issueFire_0
& (_completeMispredict_0_T | isMret | _issue_io_out_0_decoded_isFenceI
| _completeMispredict_0_T_3)),
.io_completeMispredict_1
(issueFire_1 & (_completeMispredict_1_T | isMret_1 | _completeMispredict_1_T_2)),
(issueFire_1
& (_completeMispredict_1_T | isMret_1 | _issue_io_out_1_decoded_isFenceI
| _completeMispredict_1_T_3)),
.io_completeRedirectPc_0
(isEcall | isEbreak
? _csr_io_mtvec
@@ -530,7 +630,7 @@ module OoOBackend(
? _issue_io_out_0_decoded_pc + _issue_io_out_0_decoded_immJ
: _issue_io_out_0_decoded_isJalr
? {_jalrTarget_T[63:1], 1'h0}
: _completeMispredict_0_T_2
: _completeMispredict_0_T_3
? _issue_io_out_0_decoded_pc + _issue_io_out_0_decoded_immB
: _branchRedirect_T_1),
.io_completeRedirectPc_1
@@ -542,7 +642,7 @@ module OoOBackend(
? _issue_io_out_1_decoded_pc + _issue_io_out_1_decoded_immJ
: _issue_io_out_1_decoded_isJalr
? {_jalrTarget_T_3[63:1], 1'h0}
: _completeMispredict_1_T_2
: _completeMispredict_1_T_3
? _issue_io_out_1_decoded_pc + _issue_io_out_1_decoded_immB
: _branchRedirect_T_6),
.io_completeCsrValid_0
@@ -579,6 +679,7 @@ module OoOBackend(
.io_commitEntry_0_csrCmd (_rename_io_commitEntry_0_csrCmd),
.io_commitEntry_0_csrRs1 (_rename_io_commitEntry_0_csrRs1),
.io_commitEntry_0_csrZimm (_rename_io_commitEntry_0_csrZimm),
.io_commitEntry_0_fenceI (_rename_io_commitEntry_0_fenceI),
.io_commitEntry_1_robIdx (_rename_io_commitEntry_1_robIdx),
.io_commitEntry_1_archDest (_rename_io_commitEntry_1_archDest),
.io_commitEntry_1_writesDest (_rename_io_commitEntry_1_writesDest),
@@ -595,6 +696,7 @@ module OoOBackend(
.io_commitEntry_1_csrCmd (_rename_io_commitEntry_1_csrCmd),
.io_commitEntry_1_csrRs1 (_rename_io_commitEntry_1_csrRs1),
.io_commitEntry_1_csrZimm (_rename_io_commitEntry_1_csrZimm),
.io_commitEntry_1_fenceI (_rename_io_commitEntry_1_fenceI),
.io_commitMapValid_0 (_commit_io_commitMapValid_0),
.io_commitMapValid_1 (_commit_io_commitMapValid_1),
.io_commitArch_0 (_commit_io_commitArch_0),
@@ -608,135 +710,151 @@ module OoOBackend(
.io_flush (_commit_io_flush)
);
IssueStage issue (
.clock (clock),
.reset (reset),
.io_inValid_0 (_rename_io_outValid_0),
.io_inValid_1 (_rename_io_outValid_1),
.io_in_0_decoded_pc (_rename_io_out_0_decoded_pc),
.io_in_0_decoded_inst (_rename_io_out_0_decoded_inst),
.io_in_0_decoded_rs1 (_rename_io_out_0_decoded_rs1),
.io_in_0_decoded_rs2 (_rename_io_out_0_decoded_rs2),
.io_in_0_decoded_funct3 (_rename_io_out_0_decoded_funct3),
.io_in_0_decoded_immI (_rename_io_out_0_decoded_immI),
.io_in_0_decoded_immS (_rename_io_out_0_decoded_immS),
.io_in_0_decoded_immB (_rename_io_out_0_decoded_immB),
.io_in_0_decoded_immU (_rename_io_out_0_decoded_immU),
.io_in_0_decoded_immJ (_rename_io_out_0_decoded_immJ),
.io_in_0_decoded_aluFn (_rename_io_out_0_decoded_aluFn),
.io_in_0_decoded_memWidth (_rename_io_out_0_decoded_memWidth),
.io_in_0_decoded_isLoad (_rename_io_out_0_decoded_isLoad),
.io_in_0_decoded_isStore (_rename_io_out_0_decoded_isStore),
.io_in_0_decoded_isBranch (_rename_io_out_0_decoded_isBranch),
.io_in_0_decoded_isJal (_rename_io_out_0_decoded_isJal),
.io_in_0_decoded_isJalr (_rename_io_out_0_decoded_isJalr),
.io_in_0_decoded_isLui (_rename_io_out_0_decoded_isLui),
.io_in_0_decoded_isAuipc (_rename_io_out_0_decoded_isAuipc),
.io_in_0_decoded_isOpImm (_rename_io_out_0_decoded_isOpImm),
.io_in_0_decoded_isWord (_rename_io_out_0_decoded_isWord),
.io_in_0_decoded_isSystem (_rename_io_out_0_decoded_isSystem),
.io_in_0_decoded_writesRd (_rename_io_out_0_decoded_writesRd),
.io_in_0_decoded_illegal (_rename_io_out_0_decoded_illegal),
.io_in_0_prs1 (_rename_io_out_0_prs1),
.io_in_0_prs2 (_rename_io_out_0_prs2),
.io_in_0_src1Ready (_rename_io_out_0_src1Ready),
.io_in_0_src2Ready (_rename_io_out_0_src2Ready),
.io_in_0_prd (_rename_io_out_0_prd),
.io_in_0_robIdx (_rename_io_out_0_robIdx),
.io_in_1_decoded_pc (_rename_io_out_1_decoded_pc),
.io_in_1_decoded_inst (_rename_io_out_1_decoded_inst),
.io_in_1_decoded_rs1 (_rename_io_out_1_decoded_rs1),
.io_in_1_decoded_rs2 (_rename_io_out_1_decoded_rs2),
.io_in_1_decoded_funct3 (_rename_io_out_1_decoded_funct3),
.io_in_1_decoded_immI (_rename_io_out_1_decoded_immI),
.io_in_1_decoded_immS (_rename_io_out_1_decoded_immS),
.io_in_1_decoded_immB (_rename_io_out_1_decoded_immB),
.io_in_1_decoded_immU (_rename_io_out_1_decoded_immU),
.io_in_1_decoded_immJ (_rename_io_out_1_decoded_immJ),
.io_in_1_decoded_aluFn (_rename_io_out_1_decoded_aluFn),
.io_in_1_decoded_memWidth (_rename_io_out_1_decoded_memWidth),
.io_in_1_decoded_isLoad (_rename_io_out_1_decoded_isLoad),
.io_in_1_decoded_isStore (_rename_io_out_1_decoded_isStore),
.io_in_1_decoded_isBranch (_rename_io_out_1_decoded_isBranch),
.io_in_1_decoded_isJal (_rename_io_out_1_decoded_isJal),
.io_in_1_decoded_isJalr (_rename_io_out_1_decoded_isJalr),
.io_in_1_decoded_isLui (_rename_io_out_1_decoded_isLui),
.io_in_1_decoded_isAuipc (_rename_io_out_1_decoded_isAuipc),
.io_in_1_decoded_isOpImm (_rename_io_out_1_decoded_isOpImm),
.io_in_1_decoded_isWord (_rename_io_out_1_decoded_isWord),
.io_in_1_decoded_isSystem (_rename_io_out_1_decoded_isSystem),
.io_in_1_decoded_writesRd (_rename_io_out_1_decoded_writesRd),
.io_in_1_decoded_illegal (_rename_io_out_1_decoded_illegal),
.io_in_1_prs1 (_rename_io_out_1_prs1),
.io_in_1_prs2 (_rename_io_out_1_prs2),
.io_in_1_src1Ready (_rename_io_out_1_src1Ready),
.io_in_1_src2Ready (_rename_io_out_1_src2Ready),
.io_in_1_prd (_rename_io_out_1_prd),
.io_in_1_robIdx (_rename_io_out_1_robIdx),
.io_inReady_0 (_issue_io_inReady_0),
.io_inReady_1 (_issue_io_inReady_1),
.io_wakeup_0_valid (wakeupReg_0_valid),
.io_wakeup_0_phys (wakeupReg_0_phys),
.io_wakeup_1_valid (wakeupReg_1_valid),
.io_wakeup_1_phys (wakeupReg_1_phys),
.io_outValid_0 (_issue_io_outValid_0),
.io_outValid_1 (_issue_io_outValid_1),
.io_out_0_decoded_pc (_issue_io_out_0_decoded_pc),
.io_out_0_decoded_inst (_issue_io_out_0_decoded_inst),
.io_out_0_decoded_rs1 (_issue_io_out_0_decoded_rs1),
.io_out_0_decoded_funct3 (_issue_io_out_0_decoded_funct3),
.io_out_0_decoded_immI (_issue_io_out_0_decoded_immI),
.io_out_0_decoded_immS (_issue_io_out_0_decoded_immS),
.io_out_0_decoded_immB (_issue_io_out_0_decoded_immB),
.io_out_0_decoded_immU (_issue_io_out_0_decoded_immU),
.io_out_0_decoded_immJ (_issue_io_out_0_decoded_immJ),
.io_out_0_decoded_aluFn (_issue_io_out_0_decoded_aluFn),
.io_out_0_decoded_memWidth (_issue_io_out_0_decoded_memWidth),
.io_out_0_decoded_isLoad (_issue_io_out_0_decoded_isLoad),
.io_out_0_decoded_isStore (_issue_io_out_0_decoded_isStore),
.io_out_0_decoded_isBranch (_issue_io_out_0_decoded_isBranch),
.io_out_0_decoded_isJal (_issue_io_out_0_decoded_isJal),
.io_out_0_decoded_isJalr (_issue_io_out_0_decoded_isJalr),
.io_out_0_decoded_isLui (_issue_io_out_0_decoded_isLui),
.io_out_0_decoded_isAuipc (_issue_io_out_0_decoded_isAuipc),
.io_out_0_decoded_isOpImm (_issue_io_out_0_decoded_isOpImm),
.io_out_0_decoded_isWord (_issue_io_out_0_decoded_isWord),
.io_out_0_decoded_isSystem (_issue_io_out_0_decoded_isSystem),
.io_out_0_decoded_writesRd (_issue_io_out_0_decoded_writesRd),
.io_out_0_decoded_illegal (_issue_io_out_0_decoded_illegal),
.io_out_0_prs1 (_issue_io_out_0_prs1),
.io_out_0_prs2 (_issue_io_out_0_prs2),
.io_out_0_prd (_issue_io_out_0_prd),
.io_out_0_robIdx (_issue_io_out_0_robIdx),
.io_out_1_decoded_pc (_issue_io_out_1_decoded_pc),
.io_out_1_decoded_inst (_issue_io_out_1_decoded_inst),
.io_out_1_decoded_rs1 (_issue_io_out_1_decoded_rs1),
.io_out_1_decoded_funct3 (_issue_io_out_1_decoded_funct3),
.io_out_1_decoded_immI (_issue_io_out_1_decoded_immI),
.io_out_1_decoded_immS (_issue_io_out_1_decoded_immS),
.io_out_1_decoded_immB (_issue_io_out_1_decoded_immB),
.io_out_1_decoded_immU (_issue_io_out_1_decoded_immU),
.io_out_1_decoded_immJ (_issue_io_out_1_decoded_immJ),
.io_out_1_decoded_aluFn (_issue_io_out_1_decoded_aluFn),
.io_out_1_decoded_memWidth (_issue_io_out_1_decoded_memWidth),
.io_out_1_decoded_isLoad (_issue_io_out_1_decoded_isLoad),
.io_out_1_decoded_isStore (_issue_io_out_1_decoded_isStore),
.io_out_1_decoded_isBranch (_issue_io_out_1_decoded_isBranch),
.io_out_1_decoded_isJal (_issue_io_out_1_decoded_isJal),
.io_out_1_decoded_isJalr (_issue_io_out_1_decoded_isJalr),
.io_out_1_decoded_isLui (_issue_io_out_1_decoded_isLui),
.io_out_1_decoded_isAuipc (_issue_io_out_1_decoded_isAuipc),
.io_out_1_decoded_isOpImm (_issue_io_out_1_decoded_isOpImm),
.io_out_1_decoded_isWord (_issue_io_out_1_decoded_isWord),
.io_out_1_decoded_isSystem (_issue_io_out_1_decoded_isSystem),
.io_out_1_decoded_writesRd (_issue_io_out_1_decoded_writesRd),
.io_out_1_decoded_illegal (_issue_io_out_1_decoded_illegal),
.io_out_1_prs1 (_issue_io_out_1_prs1),
.io_out_1_prs2 (_issue_io_out_1_prs2),
.io_out_1_prd (_issue_io_out_1_prd),
.io_out_1_robIdx (_issue_io_out_1_robIdx),
.io_outReady_0 (issue_io_outReady_0),
.io_outReady_1 (issue_io_outReady_1),
.io_flush (_commit_io_flush)
.clock (clock),
.reset (reset),
.io_inValid_0 (_rename_io_outValid_0),
.io_inValid_1 (_rename_io_outValid_1),
.io_in_0_decoded_pc (_rename_io_out_0_decoded_pc),
.io_in_0_decoded_inst (_rename_io_out_0_decoded_inst),
.io_in_0_decoded_rs1 (_rename_io_out_0_decoded_rs1),
.io_in_0_decoded_rs2 (_rename_io_out_0_decoded_rs2),
.io_in_0_decoded_funct3 (_rename_io_out_0_decoded_funct3),
.io_in_0_decoded_immI (_rename_io_out_0_decoded_immI),
.io_in_0_decoded_immS (_rename_io_out_0_decoded_immS),
.io_in_0_decoded_immB (_rename_io_out_0_decoded_immB),
.io_in_0_decoded_immU (_rename_io_out_0_decoded_immU),
.io_in_0_decoded_immJ (_rename_io_out_0_decoded_immJ),
.io_in_0_decoded_aluFn (_rename_io_out_0_decoded_aluFn),
.io_in_0_decoded_memWidth (_rename_io_out_0_decoded_memWidth),
.io_in_0_decoded_memSigned (_rename_io_out_0_decoded_memSigned),
.io_in_0_decoded_isLoad (_rename_io_out_0_decoded_isLoad),
.io_in_0_decoded_isStore (_rename_io_out_0_decoded_isStore),
.io_in_0_decoded_isBranch (_rename_io_out_0_decoded_isBranch),
.io_in_0_decoded_isJal (_rename_io_out_0_decoded_isJal),
.io_in_0_decoded_isJalr (_rename_io_out_0_decoded_isJalr),
.io_in_0_decoded_isLui (_rename_io_out_0_decoded_isLui),
.io_in_0_decoded_isAuipc (_rename_io_out_0_decoded_isAuipc),
.io_in_0_decoded_isOpImm (_rename_io_out_0_decoded_isOpImm),
.io_in_0_decoded_isWord (_rename_io_out_0_decoded_isWord),
.io_in_0_decoded_isSystem (_rename_io_out_0_decoded_isSystem),
.io_in_0_decoded_isFenceI (_rename_io_out_0_decoded_isFenceI),
.io_in_0_decoded_isAmo (_rename_io_out_0_decoded_isAmo),
.io_in_0_decoded_amoOp (_rename_io_out_0_decoded_amoOp),
.io_in_0_decoded_writesRd (_rename_io_out_0_decoded_writesRd),
.io_in_0_decoded_illegal (_rename_io_out_0_decoded_illegal),
.io_in_0_prs1 (_rename_io_out_0_prs1),
.io_in_0_prs2 (_rename_io_out_0_prs2),
.io_in_0_src1Ready (_rename_io_out_0_src1Ready),
.io_in_0_src2Ready (_rename_io_out_0_src2Ready),
.io_in_0_prd (_rename_io_out_0_prd),
.io_in_0_robIdx (_rename_io_out_0_robIdx),
.io_in_1_decoded_pc (_rename_io_out_1_decoded_pc),
.io_in_1_decoded_inst (_rename_io_out_1_decoded_inst),
.io_in_1_decoded_rs1 (_rename_io_out_1_decoded_rs1),
.io_in_1_decoded_rs2 (_rename_io_out_1_decoded_rs2),
.io_in_1_decoded_funct3 (_rename_io_out_1_decoded_funct3),
.io_in_1_decoded_immI (_rename_io_out_1_decoded_immI),
.io_in_1_decoded_immS (_rename_io_out_1_decoded_immS),
.io_in_1_decoded_immB (_rename_io_out_1_decoded_immB),
.io_in_1_decoded_immU (_rename_io_out_1_decoded_immU),
.io_in_1_decoded_immJ (_rename_io_out_1_decoded_immJ),
.io_in_1_decoded_aluFn (_rename_io_out_1_decoded_aluFn),
.io_in_1_decoded_memWidth (_rename_io_out_1_decoded_memWidth),
.io_in_1_decoded_memSigned (_rename_io_out_1_decoded_memSigned),
.io_in_1_decoded_isLoad (_rename_io_out_1_decoded_isLoad),
.io_in_1_decoded_isStore (_rename_io_out_1_decoded_isStore),
.io_in_1_decoded_isBranch (_rename_io_out_1_decoded_isBranch),
.io_in_1_decoded_isJal (_rename_io_out_1_decoded_isJal),
.io_in_1_decoded_isJalr (_rename_io_out_1_decoded_isJalr),
.io_in_1_decoded_isLui (_rename_io_out_1_decoded_isLui),
.io_in_1_decoded_isAuipc (_rename_io_out_1_decoded_isAuipc),
.io_in_1_decoded_isOpImm (_rename_io_out_1_decoded_isOpImm),
.io_in_1_decoded_isWord (_rename_io_out_1_decoded_isWord),
.io_in_1_decoded_isSystem (_rename_io_out_1_decoded_isSystem),
.io_in_1_decoded_isFenceI (_rename_io_out_1_decoded_isFenceI),
.io_in_1_decoded_isAmo (_rename_io_out_1_decoded_isAmo),
.io_in_1_decoded_amoOp (_rename_io_out_1_decoded_amoOp),
.io_in_1_decoded_writesRd (_rename_io_out_1_decoded_writesRd),
.io_in_1_decoded_illegal (_rename_io_out_1_decoded_illegal),
.io_in_1_prs1 (_rename_io_out_1_prs1),
.io_in_1_prs2 (_rename_io_out_1_prs2),
.io_in_1_src1Ready (_rename_io_out_1_src1Ready),
.io_in_1_src2Ready (_rename_io_out_1_src2Ready),
.io_in_1_prd (_rename_io_out_1_prd),
.io_in_1_robIdx (_rename_io_out_1_robIdx),
.io_inReady_0 (_issue_io_inReady_0),
.io_inReady_1 (_issue_io_inReady_1),
.io_wakeup_0_valid (wakeupReg_0_valid),
.io_wakeup_0_phys (wakeupReg_0_phys),
.io_wakeup_1_valid (wakeupReg_1_valid),
.io_wakeup_1_phys (wakeupReg_1_phys),
.io_outValid_0 (_issue_io_outValid_0),
.io_outValid_1 (_issue_io_outValid_1),
.io_out_0_decoded_pc (_issue_io_out_0_decoded_pc),
.io_out_0_decoded_inst (_issue_io_out_0_decoded_inst),
.io_out_0_decoded_rs1 (_issue_io_out_0_decoded_rs1),
.io_out_0_decoded_funct3 (_issue_io_out_0_decoded_funct3),
.io_out_0_decoded_immI (_issue_io_out_0_decoded_immI),
.io_out_0_decoded_immS (_issue_io_out_0_decoded_immS),
.io_out_0_decoded_immB (_issue_io_out_0_decoded_immB),
.io_out_0_decoded_immU (_issue_io_out_0_decoded_immU),
.io_out_0_decoded_immJ (_issue_io_out_0_decoded_immJ),
.io_out_0_decoded_aluFn (_issue_io_out_0_decoded_aluFn),
.io_out_0_decoded_memWidth (_issue_io_out_0_decoded_memWidth),
.io_out_0_decoded_memSigned (_issue_io_out_0_decoded_memSigned),
.io_out_0_decoded_isLoad (_issue_io_out_0_decoded_isLoad),
.io_out_0_decoded_isStore (_issue_io_out_0_decoded_isStore),
.io_out_0_decoded_isBranch (_issue_io_out_0_decoded_isBranch),
.io_out_0_decoded_isJal (_issue_io_out_0_decoded_isJal),
.io_out_0_decoded_isJalr (_issue_io_out_0_decoded_isJalr),
.io_out_0_decoded_isLui (_issue_io_out_0_decoded_isLui),
.io_out_0_decoded_isAuipc (_issue_io_out_0_decoded_isAuipc),
.io_out_0_decoded_isOpImm (_issue_io_out_0_decoded_isOpImm),
.io_out_0_decoded_isWord (_issue_io_out_0_decoded_isWord),
.io_out_0_decoded_isSystem (_issue_io_out_0_decoded_isSystem),
.io_out_0_decoded_isFenceI (_issue_io_out_0_decoded_isFenceI),
.io_out_0_decoded_isAmo (_issue_io_out_0_decoded_isAmo),
.io_out_0_decoded_amoOp (_issue_io_out_0_decoded_amoOp),
.io_out_0_decoded_writesRd (_issue_io_out_0_decoded_writesRd),
.io_out_0_decoded_illegal (_issue_io_out_0_decoded_illegal),
.io_out_0_prs1 (_issue_io_out_0_prs1),
.io_out_0_prs2 (_issue_io_out_0_prs2),
.io_out_0_prd (_issue_io_out_0_prd),
.io_out_0_robIdx (_issue_io_out_0_robIdx),
.io_out_1_decoded_pc (_issue_io_out_1_decoded_pc),
.io_out_1_decoded_inst (_issue_io_out_1_decoded_inst),
.io_out_1_decoded_rs1 (_issue_io_out_1_decoded_rs1),
.io_out_1_decoded_funct3 (_issue_io_out_1_decoded_funct3),
.io_out_1_decoded_immI (_issue_io_out_1_decoded_immI),
.io_out_1_decoded_immS (_issue_io_out_1_decoded_immS),
.io_out_1_decoded_immB (_issue_io_out_1_decoded_immB),
.io_out_1_decoded_immU (_issue_io_out_1_decoded_immU),
.io_out_1_decoded_immJ (_issue_io_out_1_decoded_immJ),
.io_out_1_decoded_aluFn (_issue_io_out_1_decoded_aluFn),
.io_out_1_decoded_memWidth (_issue_io_out_1_decoded_memWidth),
.io_out_1_decoded_memSigned (_issue_io_out_1_decoded_memSigned),
.io_out_1_decoded_isLoad (_issue_io_out_1_decoded_isLoad),
.io_out_1_decoded_isStore (_issue_io_out_1_decoded_isStore),
.io_out_1_decoded_isBranch (_issue_io_out_1_decoded_isBranch),
.io_out_1_decoded_isJal (_issue_io_out_1_decoded_isJal),
.io_out_1_decoded_isJalr (_issue_io_out_1_decoded_isJalr),
.io_out_1_decoded_isLui (_issue_io_out_1_decoded_isLui),
.io_out_1_decoded_isAuipc (_issue_io_out_1_decoded_isAuipc),
.io_out_1_decoded_isOpImm (_issue_io_out_1_decoded_isOpImm),
.io_out_1_decoded_isWord (_issue_io_out_1_decoded_isWord),
.io_out_1_decoded_isSystem (_issue_io_out_1_decoded_isSystem),
.io_out_1_decoded_isFenceI (_issue_io_out_1_decoded_isFenceI),
.io_out_1_decoded_isAmo (_issue_io_out_1_decoded_isAmo),
.io_out_1_decoded_amoOp (_issue_io_out_1_decoded_amoOp),
.io_out_1_decoded_writesRd (_issue_io_out_1_decoded_writesRd),
.io_out_1_decoded_illegal (_issue_io_out_1_decoded_illegal),
.io_out_1_prs1 (_issue_io_out_1_prs1),
.io_out_1_prs2 (_issue_io_out_1_prs2),
.io_out_1_prd (_issue_io_out_1_prd),
.io_out_1_robIdx (_issue_io_out_1_robIdx),
.io_outReady_0 (issue_io_outReady_0),
.io_outReady_1 (issue_io_outReady_1),
.io_flush (_commit_io_flush)
);
PhysicalRegFile prf (
.clock (clock),
@@ -790,10 +908,13 @@ module OoOBackend(
.io_valid
(_exec_0_io_outValid & _issue_io_out_0_decoded_writesRd
& ~_issue_io_out_0_decoded_isLoad | loadRespValid),
.io_physDest (loadRespValid ? loadPendingPhys : _issue_io_out_0_prd),
.io_physDest
(loadRespValid
? (forwardPending ? forwardPendingPhys : loadPendingPhys)
: _issue_io_out_0_prd),
.io_data
(loadRespValid
? _lsu_io_respData
? (forwardPending ? forwardPendingData : _lsu_io_respData)
: _issue_io_out_0_decoded_isLui
? _issue_io_out_0_decoded_immU
: _issue_io_out_0_decoded_isAuipc
@@ -841,6 +962,7 @@ module OoOBackend(
.io_robEntry_0_branchMispredict (_rename_io_commitEntry_0_branchMispredict),
.io_robEntry_0_redirectPc (_rename_io_commitEntry_0_redirectPc),
.io_robEntry_0_csrValid (_rename_io_commitEntry_0_csrValid),
.io_robEntry_0_fenceI (_rename_io_commitEntry_0_fenceI),
.io_robEntry_1_archDest (_rename_io_commitEntry_1_archDest),
.io_robEntry_1_writesDest (_rename_io_commitEntry_1_writesDest),
.io_robEntry_1_dest (_rename_io_commitEntry_1_dest),
@@ -851,6 +973,7 @@ module OoOBackend(
.io_robEntry_1_branchMispredict (_rename_io_commitEntry_1_branchMispredict),
.io_robEntry_1_redirectPc (_rename_io_commitEntry_1_redirectPc),
.io_robEntry_1_csrValid (_rename_io_commitEntry_1_csrValid),
.io_robEntry_1_fenceI (_rename_io_commitEntry_1_fenceI),
.io_commitReady_0 (_commit_io_commitReady_0),
.io_commitReady_1 (_commit_io_commitReady_1),
.io_freeOldPhys_0 (_commit_io_freeOldPhys_0),
@@ -867,7 +990,8 @@ module OoOBackend(
.io_redirectPc (_commit_io_redirectPc),
.io_exception (_commit_io_exception),
.io_exceptionCause (_commit_io_exceptionCause),
.io_badAddr (_commit_io_badAddr)
.io_badAddr (_commit_io_badAddr),
.io_fenceI (io_invalidateICache)
);
LoadQueue lq (
.clock (clock),
@@ -877,53 +1001,65 @@ module OoOBackend(
.io_enqIdx (_lq_io_enqIdx),
.io_addrValid (loadEnq),
.io_addrIdx (_lq_io_enqIdx),
.io_addr (_memAddr_T_1),
.io_addr (_memAddr_T_2),
.io_size (sq_io_size),
.io_complete (loadRespValid),
.io_completeIdx (loadPendingLq),
.io_completeIdx (forwardPending ? forwardPendingLq : loadPendingLq),
.io_commitValid_0 (_commitCsr0_T & _rename_io_commitEntry_0_opClass == 4'h3),
.io_commitValid_1 (_commitCsr1_T & _rename_io_commitEntry_1_opClass == 4'h3),
.io_commitRobIdx_0 (_rename_io_commitEntry_0_robIdx),
.io_commitRobIdx_1 (_rename_io_commitEntry_1_robIdx),
.io_storeAddrValid (storeEnq),
.io_storeRobIdx (sq_io_enqRobIdx),
.io_storeAddr (_memAddr_T_1),
.io_storeAddr (_memAddr_T_2),
.io_storeSize (sq_io_size),
.io_violation (_lq_io_violation),
.io_flush (_commit_io_flush)
);
StoreQueue sq (
.clock (clock),
.reset (reset),
.io_enqValid (storeEnq),
.io_enqRobIdx (sq_io_enqRobIdx),
.io_enqIdx (_sq_io_enqIdx),
.io_writeAddr (storeEnq),
.io_writeData (storeEnq),
.io_writeIdx (_sq_io_enqIdx),
.io_addr (_memAddr_T_1),
.io_data (memIssue_0 ? _prf_io_rdata_1 : _prf_io_rdata_3),
.io_size (sq_io_size),
.io_loadAddr (_memAddr_T_1),
.io_loadRobIdx (sq_io_enqRobIdx),
.io_forwardValid (_sq_io_forwardValid),
.clock (clock),
.reset (reset),
.io_enqValid (storeEnq),
.io_enqRobIdx (sq_io_enqRobIdx),
.io_enqIdx (_sq_io_enqIdx),
.io_writeAddr (storeEnq),
.io_writeData (storeEnq),
.io_writeIdx (_sq_io_enqIdx),
.io_addr (_memAddr_T_2),
.io_data (memSrc2),
.io_size (sq_io_size),
.io_loadAddr (_memAddr_T_2),
.io_loadSize (sq_io_size),
.io_loadRobIdx (sq_io_enqRobIdx),
.io_forwardValid (_sq_io_forwardValid),
.io_forwardData (_sq_io_forwardData),
.io_forwardBlock (_sq_io_forwardBlock),
.io_olderStoreValid (_sq_io_olderStoreValid),
.io_commitValid
(commitStore0 | _commitCsr1_T & _rename_io_commitEntry_1_opClass == 4'h4),
.io_commitRobIdx
(commitStore0 ? _rename_io_commitEntry_0_robIdx : _rename_io_commitEntry_1_robIdx),
.io_drainValid (_sq_io_drainValid),
.io_drain_addr (_sq_io_drain_addr),
.io_drain_data (_sq_io_drain_data),
.io_drain_size (_sq_io_drain_size),
.io_drainReady (~lsuLoadReq & _lsu_io_reqReady),
.io_flush (_commit_io_flush)
.io_drainValid (_sq_io_drainValid),
.io_drain_addr (_sq_io_drain_addr),
.io_drain_data (_sq_io_drain_data),
.io_drain_size (_sq_io_drain_size),
.io_drainReady (~lsuLoadReq & _lsu_io_reqReady),
.io_flush (_commit_io_flush)
);
LSU lsu (
.clock (clock),
.reset (reset),
.io_reqValid (lsuLoadReq | _sq_io_drainValid),
.io_req_addr
(lsuLoadReq ? _memAddr_T_1 : _sq_io_drainValid ? _sq_io_drain_addr : 64'h0),
.io_req_data (lsuLoadReq | ~_sq_io_drainValid ? 64'h0 : _sq_io_drain_data),
.io_req_isStore (~lsuLoadReq & _sq_io_drainValid),
.io_req_size
(lsuLoadReq ? sq_io_size : _sq_io_drainValid ? _sq_io_drain_size : 3'h0),
.io_req_addr (lsuLoadReq ? _memAddr_T_2 : _sq_io_drain_addr),
.io_req_data (lsuLoadReq ? memSrc2 : _sq_io_drain_data),
.io_req_isStore (~lsuLoadReq),
.io_req_isSigned (lsuLoadReq & (_GEN | loadReq_isAmo)),
.io_req_isAmo (lsuLoadReq & loadReq_isAmo),
.io_req_amoOp
(lsuLoadReq
? (memIssue_0 ? _issue_io_out_0_decoded_amoOp : _issue_io_out_1_decoded_amoOp)
: 5'h0),
.io_req_size (lsuLoadReq ? sq_io_size : _sq_io_drain_size),
.io_reqReady (_lsu_io_reqReady),
.io_satp (_csr_io_satp),
.io_dmemReqValid (io_dmemReqValid),

4009
generated-ooo/ROB.sv
View File

File diff suppressed because it is too large Load Diff

66
generated-ooo/RenameStage.sv
View File

@@ -18,7 +18,8 @@ module RenameStage(
input [3:0] io_in_0_opClass,
input [4:0] io_in_0_aluFn,
input [2:0] io_in_0_memWidth,
input io_in_0_isLoad,
input io_in_0_memSigned,
io_in_0_isLoad,
io_in_0_isStore,
io_in_0_isBranch,
io_in_0_isJal,
@@ -28,7 +29,10 @@ module RenameStage(
io_in_0_isOpImm,
io_in_0_isWord,
io_in_0_isSystem,
io_in_0_writesRd,
io_in_0_isFenceI,
io_in_0_isAmo,
input [4:0] io_in_0_amoOp,
input io_in_0_writesRd,
io_in_0_illegal,
input [63:0] io_in_1_pc,
input [31:0] io_in_1_inst,
@@ -44,7 +48,8 @@ module RenameStage(
input [3:0] io_in_1_opClass,
input [4:0] io_in_1_aluFn,
input [2:0] io_in_1_memWidth,
input io_in_1_isLoad,
input io_in_1_memSigned,
io_in_1_isLoad,
io_in_1_isStore,
io_in_1_isBranch,
io_in_1_isJal,
@@ -54,7 +59,10 @@ module RenameStage(
io_in_1_isOpImm,
io_in_1_isWord,
io_in_1_isSystem,
io_in_1_writesRd,
io_in_1_isFenceI,
io_in_1_isAmo,
input [4:0] io_in_1_amoOp,
input io_in_1_writesRd,
io_in_1_illegal,
output io_outValid_0,
io_outValid_1,
@@ -70,7 +78,8 @@ module RenameStage(
io_out_0_decoded_immJ,
output [4:0] io_out_0_decoded_aluFn,
output [2:0] io_out_0_decoded_memWidth,
output io_out_0_decoded_isLoad,
output io_out_0_decoded_memSigned,
io_out_0_decoded_isLoad,
io_out_0_decoded_isStore,
io_out_0_decoded_isBranch,
io_out_0_decoded_isJal,
@@ -80,7 +89,10 @@ module RenameStage(
io_out_0_decoded_isOpImm,
io_out_0_decoded_isWord,
io_out_0_decoded_isSystem,
io_out_0_decoded_writesRd,
io_out_0_decoded_isFenceI,
io_out_0_decoded_isAmo,
output [4:0] io_out_0_decoded_amoOp,
output io_out_0_decoded_writesRd,
io_out_0_decoded_illegal,
output [5:0] io_out_0_prs1,
io_out_0_prs2,
@@ -100,7 +112,8 @@ module RenameStage(
io_out_1_decoded_immJ,
output [4:0] io_out_1_decoded_aluFn,
output [2:0] io_out_1_decoded_memWidth,
output io_out_1_decoded_isLoad,
output io_out_1_decoded_memSigned,
io_out_1_decoded_isLoad,
io_out_1_decoded_isStore,
io_out_1_decoded_isBranch,
io_out_1_decoded_isJal,
@@ -110,7 +123,10 @@ module RenameStage(
io_out_1_decoded_isOpImm,
io_out_1_decoded_isWord,
io_out_1_decoded_isSystem,
io_out_1_decoded_writesRd,
io_out_1_decoded_isFenceI,
io_out_1_decoded_isAmo,
output [4:0] io_out_1_decoded_amoOp,
output io_out_1_decoded_writesRd,
io_out_1_decoded_illegal,
output [5:0] io_out_1_prs1,
io_out_1_prs2,
@@ -167,6 +183,7 @@ module RenameStage(
output [2:0] io_commitEntry_0_csrCmd,
output [63:0] io_commitEntry_0_csrRs1,
output [4:0] io_commitEntry_0_csrZimm,
output io_commitEntry_0_fenceI,
output [5:0] io_commitEntry_1_robIdx,
output [4:0] io_commitEntry_1_archDest,
output io_commitEntry_1_writesDest,
@@ -183,6 +200,7 @@ module RenameStage(
output [2:0] io_commitEntry_1_csrCmd,
output [63:0] io_commitEntry_1_csrRs1,
output [4:0] io_commitEntry_1_csrZimm,
output io_commitEntry_1_fenceI,
input io_commitMapValid_0,
io_commitMapValid_1,
input [4:0] io_commitArch_0,
@@ -880,11 +898,13 @@ module RenameStage(
.io_allocateEntry_0_opClass (io_in_0_opClass),
.io_allocateEntry_0_dest (e_dest),
.io_allocateEntry_0_oldDest (_table_io_oldPrd_0),
.io_allocateEntry_0_fenceI (io_in_0_isFenceI),
.io_allocateEntry_1_archDest (io_in_1_rd),
.io_allocateEntry_1_writesDest (io_in_1_writesRd),
.io_allocateEntry_1_opClass (io_in_1_opClass),
.io_allocateEntry_1_dest (e_1_dest),
.io_allocateEntry_1_oldDest (_table_io_oldPrd_1),
.io_allocateEntry_1_fenceI (io_in_1_isFenceI),
.io_allocateIdx_0 (io_out_0_robIdx),
.io_allocateIdx_1 (io_out_1_robIdx),
.io_canAllocate (_rob_io_canAllocate),
@@ -930,6 +950,7 @@ module RenameStage(
.io_commit_0_csrCmd (io_commitEntry_0_csrCmd),
.io_commit_0_csrRs1 (io_commitEntry_0_csrRs1),
.io_commit_0_csrZimm (io_commitEntry_0_csrZimm),
.io_commit_0_fenceI (io_commitEntry_0_fenceI),
.io_commit_1_robIdx (io_commitEntry_1_robIdx),
.io_commit_1_archDest (io_commitEntry_1_archDest),
.io_commit_1_writesDest (io_commitEntry_1_writesDest),
@@ -946,6 +967,7 @@ module RenameStage(
.io_commit_1_csrCmd (io_commitEntry_1_csrCmd),
.io_commit_1_csrRs1 (io_commitEntry_1_csrRs1),
.io_commit_1_csrZimm (io_commitEntry_1_csrZimm),
.io_commit_1_fenceI (io_commitEntry_1_fenceI),
.io_commitReady_0 (io_commitReady_0),
.io_commitReady_1 (io_commitReady_1),
.io_flush (io_flush)
@@ -964,6 +986,7 @@ module RenameStage(
assign io_out_0_decoded_immJ = io_in_0_immJ;
assign io_out_0_decoded_aluFn = io_in_0_aluFn;
assign io_out_0_decoded_memWidth = io_in_0_memWidth;
assign io_out_0_decoded_memSigned = io_in_0_memSigned;
assign io_out_0_decoded_isLoad = io_in_0_isLoad;
assign io_out_0_decoded_isStore = io_in_0_isStore;
assign io_out_0_decoded_isBranch = io_in_0_isBranch;
@@ -974,12 +997,23 @@ module RenameStage(
assign io_out_0_decoded_isOpImm = io_in_0_isOpImm;
assign io_out_0_decoded_isWord = io_in_0_isWord;
assign io_out_0_decoded_isSystem = io_in_0_isSystem;
assign io_out_0_decoded_isFenceI = io_in_0_isFenceI;
assign io_out_0_decoded_isAmo = io_in_0_isAmo;
assign io_out_0_decoded_amoOp = io_in_0_amoOp;
assign io_out_0_decoded_writesRd = io_in_0_writesRd;
assign io_out_0_decoded_illegal = io_in_0_illegal;
assign io_out_0_prs1 = _table_io_prs1_0;
assign io_out_0_prs2 = _table_io_prs2_0;
assign io_out_0_src1Ready = io_in_0_rs1 == 5'h0 | _GEN[_table_io_prs1_0];
assign io_out_0_src2Ready = io_in_0_rs2 == 5'h0 | _GEN[_table_io_prs2_0];
assign io_out_0_src1Ready =
|{io_in_0_rs1 == 5'h0,
_GEN[_table_io_prs1_0],
io_wbValid_1 & io_wbPhys_1 == _table_io_prs1_0,
io_wbValid_0 & io_wbPhys_0 == _table_io_prs1_0};
assign io_out_0_src2Ready =
|{io_in_0_rs2 == 5'h0,
_GEN[_table_io_prs2_0],
io_wbValid_1 & io_wbPhys_1 == _table_io_prs2_0,
io_wbValid_0 & io_wbPhys_0 == _table_io_prs2_0};
assign io_out_0_prd = e_dest;
assign io_out_1_decoded_pc = io_in_1_pc;
assign io_out_1_decoded_inst = io_in_1_inst;
@@ -993,6 +1027,7 @@ module RenameStage(
assign io_out_1_decoded_immJ = io_in_1_immJ;
assign io_out_1_decoded_aluFn = io_in_1_aluFn;
assign io_out_1_decoded_memWidth = io_in_1_memWidth;
assign io_out_1_decoded_memSigned = io_in_1_memSigned;
assign io_out_1_decoded_isLoad = io_in_1_isLoad;
assign io_out_1_decoded_isStore = io_in_1_isStore;
assign io_out_1_decoded_isBranch = io_in_1_isBranch;
@@ -1003,16 +1038,23 @@ module RenameStage(
assign io_out_1_decoded_isOpImm = io_in_1_isOpImm;
assign io_out_1_decoded_isWord = io_in_1_isWord;
assign io_out_1_decoded_isSystem = io_in_1_isSystem;
assign io_out_1_decoded_isFenceI = io_in_1_isFenceI;
assign io_out_1_decoded_isAmo = io_in_1_isAmo;
assign io_out_1_decoded_amoOp = io_in_1_amoOp;
assign io_out_1_decoded_writesRd = io_in_1_writesRd;
assign io_out_1_decoded_illegal = io_in_1_illegal;
assign io_out_1_prs1 = _table_io_prs1_1;
assign io_out_1_prs2 = _table_io_prs2_1;
assign io_out_1_src1Ready =
io_in_1_rs1 == 5'h0 | ~(table_io_wen_0 & (|io_in_0_rd) & io_in_0_rd == io_in_1_rs1)
& _GEN[_table_io_prs1_1];
& (|{_GEN[_table_io_prs1_1],
io_wbValid_1 & io_wbPhys_1 == _table_io_prs1_1,
io_wbValid_0 & io_wbPhys_0 == _table_io_prs1_1});
assign io_out_1_src2Ready =
io_in_1_rs2 == 5'h0 | ~(table_io_wen_0 & (|io_in_0_rd) & io_in_0_rd == io_in_1_rs2)
& _GEN[_table_io_prs2_1];
& (|{_GEN[_table_io_prs2_1],
io_wbValid_1 & io_wbPhys_1 == _table_io_prs2_1,
io_wbValid_0 & io_wbPhys_0 == _table_io_prs2_1});
assign io_out_1_prd = e_1_dest;
assign io_canAccept = {1'h0, io_inValid_0} + {1'h0, io_inValid_1} == 2'h0 | canRename;
endmodule

671
generated-ooo/RenameTable.sv
View File

@@ -123,7 +123,137 @@ module RenameTable(
reg [5:0] committed_29;
reg [5:0] committed_30;
reg [5:0] committed_31;
wire [31:0][5:0] _GEN =
wire _GEN = io_commitWen_0 & (|io_commitRd_0);
wire _GEN_0 = _GEN & ~(|io_commitRd_0);
wire _GEN_1 = _GEN & io_commitRd_0 == 5'h1;
wire _GEN_2 = _GEN & io_commitRd_0 == 5'h2;
wire _GEN_3 = _GEN & io_commitRd_0 == 5'h3;
wire _GEN_4 = _GEN & io_commitRd_0 == 5'h4;
wire _GEN_5 = _GEN & io_commitRd_0 == 5'h5;
wire _GEN_6 = _GEN & io_commitRd_0 == 5'h6;
wire _GEN_7 = _GEN & io_commitRd_0 == 5'h7;
wire _GEN_8 = _GEN & io_commitRd_0 == 5'h8;
wire _GEN_9 = _GEN & io_commitRd_0 == 5'h9;
wire _GEN_10 = _GEN & io_commitRd_0 == 5'hA;
wire _GEN_11 = _GEN & io_commitRd_0 == 5'hB;
wire _GEN_12 = _GEN & io_commitRd_0 == 5'hC;
wire _GEN_13 = _GEN & io_commitRd_0 == 5'hD;
wire _GEN_14 = _GEN & io_commitRd_0 == 5'hE;
wire _GEN_15 = _GEN & io_commitRd_0 == 5'hF;
wire _GEN_16 = _GEN & io_commitRd_0 == 5'h10;
wire _GEN_17 = _GEN & io_commitRd_0 == 5'h11;
wire _GEN_18 = _GEN & io_commitRd_0 == 5'h12;
wire _GEN_19 = _GEN & io_commitRd_0 == 5'h13;
wire _GEN_20 = _GEN & io_commitRd_0 == 5'h14;
wire _GEN_21 = _GEN & io_commitRd_0 == 5'h15;
wire _GEN_22 = _GEN & io_commitRd_0 == 5'h16;
wire _GEN_23 = _GEN & io_commitRd_0 == 5'h17;
wire _GEN_24 = _GEN & io_commitRd_0 == 5'h18;
wire _GEN_25 = _GEN & io_commitRd_0 == 5'h19;
wire _GEN_26 = _GEN & io_commitRd_0 == 5'h1A;
wire _GEN_27 = _GEN & io_commitRd_0 == 5'h1B;
wire _GEN_28 = _GEN & io_commitRd_0 == 5'h1C;
wire _GEN_29 = _GEN & io_commitRd_0 == 5'h1D;
wire _GEN_30 = _GEN & io_commitRd_0 == 5'h1E;
wire _GEN_31 = _GEN & (&io_commitRd_0);
wire _GEN_32 = io_commitWen_1 & (|io_commitRd_1);
wire _GEN_33 = _GEN_32 & ~(|io_commitRd_1);
wire [5:0] committedNext_0 =
_GEN_33 ? io_commitPhys_1 : _GEN_0 ? io_commitPhys_0 : committed_0;
wire _GEN_34 = _GEN_32 & io_commitRd_1 == 5'h1;
wire [5:0] committedNext_1 =
_GEN_34 ? io_commitPhys_1 : _GEN_1 ? io_commitPhys_0 : committed_1;
wire _GEN_35 = _GEN_32 & io_commitRd_1 == 5'h2;
wire [5:0] committedNext_2 =
_GEN_35 ? io_commitPhys_1 : _GEN_2 ? io_commitPhys_0 : committed_2;
wire _GEN_36 = _GEN_32 & io_commitRd_1 == 5'h3;
wire [5:0] committedNext_3 =
_GEN_36 ? io_commitPhys_1 : _GEN_3 ? io_commitPhys_0 : committed_3;
wire _GEN_37 = _GEN_32 & io_commitRd_1 == 5'h4;
wire [5:0] committedNext_4 =
_GEN_37 ? io_commitPhys_1 : _GEN_4 ? io_commitPhys_0 : committed_4;
wire _GEN_38 = _GEN_32 & io_commitRd_1 == 5'h5;
wire [5:0] committedNext_5 =
_GEN_38 ? io_commitPhys_1 : _GEN_5 ? io_commitPhys_0 : committed_5;
wire _GEN_39 = _GEN_32 & io_commitRd_1 == 5'h6;
wire [5:0] committedNext_6 =
_GEN_39 ? io_commitPhys_1 : _GEN_6 ? io_commitPhys_0 : committed_6;
wire _GEN_40 = _GEN_32 & io_commitRd_1 == 5'h7;
wire [5:0] committedNext_7 =
_GEN_40 ? io_commitPhys_1 : _GEN_7 ? io_commitPhys_0 : committed_7;
wire _GEN_41 = _GEN_32 & io_commitRd_1 == 5'h8;
wire [5:0] committedNext_8 =
_GEN_41 ? io_commitPhys_1 : _GEN_8 ? io_commitPhys_0 : committed_8;
wire _GEN_42 = _GEN_32 & io_commitRd_1 == 5'h9;
wire [5:0] committedNext_9 =
_GEN_42 ? io_commitPhys_1 : _GEN_9 ? io_commitPhys_0 : committed_9;
wire _GEN_43 = _GEN_32 & io_commitRd_1 == 5'hA;
wire [5:0] committedNext_10 =
_GEN_43 ? io_commitPhys_1 : _GEN_10 ? io_commitPhys_0 : committed_10;
wire _GEN_44 = _GEN_32 & io_commitRd_1 == 5'hB;
wire [5:0] committedNext_11 =
_GEN_44 ? io_commitPhys_1 : _GEN_11 ? io_commitPhys_0 : committed_11;
wire _GEN_45 = _GEN_32 & io_commitRd_1 == 5'hC;
wire [5:0] committedNext_12 =
_GEN_45 ? io_commitPhys_1 : _GEN_12 ? io_commitPhys_0 : committed_12;
wire _GEN_46 = _GEN_32 & io_commitRd_1 == 5'hD;
wire [5:0] committedNext_13 =
_GEN_46 ? io_commitPhys_1 : _GEN_13 ? io_commitPhys_0 : committed_13;
wire _GEN_47 = _GEN_32 & io_commitRd_1 == 5'hE;
wire [5:0] committedNext_14 =
_GEN_47 ? io_commitPhys_1 : _GEN_14 ? io_commitPhys_0 : committed_14;
wire _GEN_48 = _GEN_32 & io_commitRd_1 == 5'hF;
wire [5:0] committedNext_15 =
_GEN_48 ? io_commitPhys_1 : _GEN_15 ? io_commitPhys_0 : committed_15;
wire _GEN_49 = _GEN_32 & io_commitRd_1 == 5'h10;
wire [5:0] committedNext_16 =
_GEN_49 ? io_commitPhys_1 : _GEN_16 ? io_commitPhys_0 : committed_16;
wire _GEN_50 = _GEN_32 & io_commitRd_1 == 5'h11;
wire [5:0] committedNext_17 =
_GEN_50 ? io_commitPhys_1 : _GEN_17 ? io_commitPhys_0 : committed_17;
wire _GEN_51 = _GEN_32 & io_commitRd_1 == 5'h12;
wire [5:0] committedNext_18 =
_GEN_51 ? io_commitPhys_1 : _GEN_18 ? io_commitPhys_0 : committed_18;
wire _GEN_52 = _GEN_32 & io_commitRd_1 == 5'h13;
wire [5:0] committedNext_19 =
_GEN_52 ? io_commitPhys_1 : _GEN_19 ? io_commitPhys_0 : committed_19;
wire _GEN_53 = _GEN_32 & io_commitRd_1 == 5'h14;
wire [5:0] committedNext_20 =
_GEN_53 ? io_commitPhys_1 : _GEN_20 ? io_commitPhys_0 : committed_20;
wire _GEN_54 = _GEN_32 & io_commitRd_1 == 5'h15;
wire [5:0] committedNext_21 =
_GEN_54 ? io_commitPhys_1 : _GEN_21 ? io_commitPhys_0 : committed_21;
wire _GEN_55 = _GEN_32 & io_commitRd_1 == 5'h16;
wire [5:0] committedNext_22 =
_GEN_55 ? io_commitPhys_1 : _GEN_22 ? io_commitPhys_0 : committed_22;
wire _GEN_56 = _GEN_32 & io_commitRd_1 == 5'h17;
wire [5:0] committedNext_23 =
_GEN_56 ? io_commitPhys_1 : _GEN_23 ? io_commitPhys_0 : committed_23;
wire _GEN_57 = _GEN_32 & io_commitRd_1 == 5'h18;
wire [5:0] committedNext_24 =
_GEN_57 ? io_commitPhys_1 : _GEN_24 ? io_commitPhys_0 : committed_24;
wire _GEN_58 = _GEN_32 & io_commitRd_1 == 5'h19;
wire [5:0] committedNext_25 =
_GEN_58 ? io_commitPhys_1 : _GEN_25 ? io_commitPhys_0 : committed_25;
wire _GEN_59 = _GEN_32 & io_commitRd_1 == 5'h1A;
wire [5:0] committedNext_26 =
_GEN_59 ? io_commitPhys_1 : _GEN_26 ? io_commitPhys_0 : committed_26;
wire _GEN_60 = _GEN_32 & io_commitRd_1 == 5'h1B;
wire [5:0] committedNext_27 =
_GEN_60 ? io_commitPhys_1 : _GEN_27 ? io_commitPhys_0 : committed_27;
wire _GEN_61 = _GEN_32 & io_commitRd_1 == 5'h1C;
wire [5:0] committedNext_28 =
_GEN_61 ? io_commitPhys_1 : _GEN_28 ? io_commitPhys_0 : committed_28;
wire _GEN_62 = _GEN_32 & io_commitRd_1 == 5'h1D;
wire [5:0] committedNext_29 =
_GEN_62 ? io_commitPhys_1 : _GEN_29 ? io_commitPhys_0 : committed_29;
wire _GEN_63 = _GEN_32 & io_commitRd_1 == 5'h1E;
wire [5:0] committedNext_30 =
_GEN_63 ? io_commitPhys_1 : _GEN_30 ? io_commitPhys_0 : committed_30;
wire _GEN_64 = _GEN_32 & (&io_commitRd_1);
wire [5:0] committedNext_31 =
_GEN_64 ? io_commitPhys_1 : _GEN_31 ? io_commitPhys_0 : committed_31;
wire [31:0][5:0] _GEN_65 =
{{speculative_31},
{speculative_30},
{speculative_29},
@@ -224,342 +354,341 @@ module RenameTable(
committed_30 <= 6'h1E;
committed_31 <= 6'h1F;
end
else if (io_recover) begin
speculative_0 <= committed_0;
speculative_1 <= committed_1;
speculative_2 <= committed_2;
speculative_3 <= committed_3;
speculative_4 <= committed_4;
speculative_5 <= committed_5;
speculative_6 <= committed_6;
speculative_7 <= committed_7;
speculative_8 <= committed_8;
speculative_9 <= committed_9;
speculative_10 <= committed_10;
speculative_11 <= committed_11;
speculative_12 <= committed_12;
speculative_13 <= committed_13;
speculative_14 <= committed_14;
speculative_15 <= committed_15;
speculative_16 <= committed_16;
speculative_17 <= committed_17;
speculative_18 <= committed_18;
speculative_19 <= committed_19;
speculative_20 <= committed_20;
speculative_21 <= committed_21;
speculative_22 <= committed_22;
speculative_23 <= committed_23;
speculative_24 <= committed_24;
speculative_25 <= committed_25;
speculative_26 <= committed_26;
speculative_27 <= committed_27;
speculative_28 <= committed_28;
speculative_29 <= committed_29;
speculative_30 <= committed_30;
speculative_31 <= committed_31;
end
else begin
automatic logic _GEN_0;
automatic logic _GEN_1;
automatic logic _GEN_2 = io_wen_1 & (|io_rd_1);
automatic logic _GEN_3 = io_commitWen_1 & (|io_commitRd_1);
_GEN_0 = io_wen_0 & (|io_rd_0);
_GEN_1 = io_commitWen_0 & (|io_commitRd_0);
if (_GEN_2 & ~(|io_rd_1))
speculative_0 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h0)
speculative_0 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1)
speculative_1 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1)
speculative_1 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h2)
speculative_2 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h2)
speculative_2 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h3)
speculative_3 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h3)
speculative_3 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h4)
speculative_4 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h4)
speculative_4 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h5)
speculative_5 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h5)
speculative_5 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h6)
speculative_6 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h6)
speculative_6 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h7)
speculative_7 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h7)
speculative_7 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h8)
speculative_8 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h8)
speculative_8 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h9)
speculative_9 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h9)
speculative_9 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hA)
speculative_10 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hA)
speculative_10 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hB)
speculative_11 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hB)
speculative_11 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hC)
speculative_12 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hC)
speculative_12 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hD)
speculative_13 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hD)
speculative_13 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hE)
speculative_14 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hE)
speculative_14 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'hF)
speculative_15 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'hF)
speculative_15 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h10)
speculative_16 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h10)
speculative_16 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h11)
speculative_17 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h11)
speculative_17 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h12)
speculative_18 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h12)
speculative_18 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h13)
speculative_19 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h13)
speculative_19 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h14)
speculative_20 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h14)
speculative_20 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h15)
speculative_21 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h15)
speculative_21 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h16)
speculative_22 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h16)
speculative_22 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h17)
speculative_23 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h17)
speculative_23 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h18)
speculative_24 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h18)
speculative_24 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h19)
speculative_25 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h19)
speculative_25 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1A)
speculative_26 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1A)
speculative_26 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1B)
speculative_27 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1B)
speculative_27 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1C)
speculative_28 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1C)
speculative_28 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1D)
speculative_29 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1D)
speculative_29 <= io_newPhys_0;
if (_GEN_2 & io_rd_1 == 5'h1E)
speculative_30 <= io_newPhys_1;
else if (_GEN_0 & io_rd_0 == 5'h1E)
speculative_30 <= io_newPhys_0;
if (_GEN_2 & (&io_rd_1))
speculative_31 <= io_newPhys_1;
else if (_GEN_0 & (&io_rd_0))
speculative_31 <= io_newPhys_0;
if (_GEN_3 & ~(|io_commitRd_1))
if (io_recover) begin
speculative_0 <= committedNext_0;
speculative_1 <= committedNext_1;
speculative_2 <= committedNext_2;
speculative_3 <= committedNext_3;
speculative_4 <= committedNext_4;
speculative_5 <= committedNext_5;
speculative_6 <= committedNext_6;
speculative_7 <= committedNext_7;
speculative_8 <= committedNext_8;
speculative_9 <= committedNext_9;
speculative_10 <= committedNext_10;
speculative_11 <= committedNext_11;
speculative_12 <= committedNext_12;
speculative_13 <= committedNext_13;
speculative_14 <= committedNext_14;
speculative_15 <= committedNext_15;
speculative_16 <= committedNext_16;
speculative_17 <= committedNext_17;
speculative_18 <= committedNext_18;
speculative_19 <= committedNext_19;
speculative_20 <= committedNext_20;
speculative_21 <= committedNext_21;
speculative_22 <= committedNext_22;
speculative_23 <= committedNext_23;
speculative_24 <= committedNext_24;
speculative_25 <= committedNext_25;
speculative_26 <= committedNext_26;
speculative_27 <= committedNext_27;
speculative_28 <= committedNext_28;
speculative_29 <= committedNext_29;
speculative_30 <= committedNext_30;
speculative_31 <= committedNext_31;
end
else begin
automatic logic _GEN_66;
automatic logic _GEN_67 = io_wen_1 & (|io_rd_1);
_GEN_66 = io_wen_0 & (|io_rd_0);
if (_GEN_67 & ~(|io_rd_1))
speculative_0 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h0)
speculative_0 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h1)
speculative_1 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h1)
speculative_1 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h2)
speculative_2 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h2)
speculative_2 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h3)
speculative_3 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h3)
speculative_3 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h4)
speculative_4 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h4)
speculative_4 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h5)
speculative_5 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h5)
speculative_5 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h6)
speculative_6 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h6)
speculative_6 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h7)
speculative_7 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h7)
speculative_7 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h8)
speculative_8 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h8)
speculative_8 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h9)
speculative_9 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h9)
speculative_9 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'hA)
speculative_10 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'hA)
speculative_10 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'hB)
speculative_11 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'hB)
speculative_11 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'hC)
speculative_12 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'hC)
speculative_12 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'hD)
speculative_13 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'hD)
speculative_13 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'hE)
speculative_14 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'hE)
speculative_14 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'hF)
speculative_15 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'hF)
speculative_15 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h10)
speculative_16 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h10)
speculative_16 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h11)
speculative_17 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h11)
speculative_17 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h12)
speculative_18 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h12)
speculative_18 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h13)
speculative_19 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h13)
speculative_19 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h14)
speculative_20 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h14)
speculative_20 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h15)
speculative_21 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h15)
speculative_21 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h16)
speculative_22 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h16)
speculative_22 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h17)
speculative_23 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h17)
speculative_23 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h18)
speculative_24 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h18)
speculative_24 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h19)
speculative_25 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h19)
speculative_25 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h1A)
speculative_26 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h1A)
speculative_26 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h1B)
speculative_27 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h1B)
speculative_27 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h1C)
speculative_28 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h1C)
speculative_28 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h1D)
speculative_29 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h1D)
speculative_29 <= io_newPhys_0;
if (_GEN_67 & io_rd_1 == 5'h1E)
speculative_30 <= io_newPhys_1;
else if (_GEN_66 & io_rd_0 == 5'h1E)
speculative_30 <= io_newPhys_0;
if (_GEN_67 & (&io_rd_1))
speculative_31 <= io_newPhys_1;
else if (_GEN_66 & (&io_rd_0))
speculative_31 <= io_newPhys_0;
end
if (_GEN_33)
committed_0 <= io_commitPhys_1;
else if (_GEN_1 & ~(|io_commitRd_0))
else if (_GEN_0)
committed_0 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1)
if (_GEN_34)
committed_1 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1)
else if (_GEN_1)
committed_1 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h2)
if (_GEN_35)
committed_2 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h2)
else if (_GEN_2)
committed_2 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h3)
if (_GEN_36)
committed_3 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h3)
else if (_GEN_3)
committed_3 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h4)
if (_GEN_37)
committed_4 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h4)
else if (_GEN_4)
committed_4 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h5)
if (_GEN_38)
committed_5 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h5)
else if (_GEN_5)
committed_5 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h6)
if (_GEN_39)
committed_6 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h6)
else if (_GEN_6)
committed_6 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h7)
if (_GEN_40)
committed_7 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h7)
else if (_GEN_7)
committed_7 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h8)
if (_GEN_41)
committed_8 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h8)
else if (_GEN_8)
committed_8 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h9)
if (_GEN_42)
committed_9 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h9)
else if (_GEN_9)
committed_9 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hA)
if (_GEN_43)
committed_10 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hA)
else if (_GEN_10)
committed_10 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hB)
if (_GEN_44)
committed_11 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hB)
else if (_GEN_11)
committed_11 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hC)
if (_GEN_45)
committed_12 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hC)
else if (_GEN_12)
committed_12 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hD)
if (_GEN_46)
committed_13 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hD)
else if (_GEN_13)
committed_13 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hE)
if (_GEN_47)
committed_14 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hE)
else if (_GEN_14)
committed_14 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'hF)
if (_GEN_48)
committed_15 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'hF)
else if (_GEN_15)
committed_15 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h10)
if (_GEN_49)
committed_16 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h10)
else if (_GEN_16)
committed_16 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h11)
if (_GEN_50)
committed_17 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h11)
else if (_GEN_17)
committed_17 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h12)
if (_GEN_51)
committed_18 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h12)
else if (_GEN_18)
committed_18 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h13)
if (_GEN_52)
committed_19 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h13)
else if (_GEN_19)
committed_19 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h14)
if (_GEN_53)
committed_20 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h14)
else if (_GEN_20)
committed_20 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h15)
if (_GEN_54)
committed_21 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h15)
else if (_GEN_21)
committed_21 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h16)
if (_GEN_55)
committed_22 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h16)
else if (_GEN_22)
committed_22 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h17)
if (_GEN_56)
committed_23 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h17)
else if (_GEN_23)
committed_23 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h18)
if (_GEN_57)
committed_24 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h18)
else if (_GEN_24)
committed_24 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h19)
if (_GEN_58)
committed_25 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h19)
else if (_GEN_25)
committed_25 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1A)
if (_GEN_59)
committed_26 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1A)
else if (_GEN_26)
committed_26 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1B)
if (_GEN_60)
committed_27 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1B)
else if (_GEN_27)
committed_27 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1C)
if (_GEN_61)
committed_28 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1C)
else if (_GEN_28)
committed_28 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1D)
if (_GEN_62)
committed_29 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1D)
else if (_GEN_29)
committed_29 <= io_commitPhys_0;
if (_GEN_3 & io_commitRd_1 == 5'h1E)
if (_GEN_63)
committed_30 <= io_commitPhys_1;
else if (_GEN_1 & io_commitRd_0 == 5'h1E)
else if (_GEN_30)
committed_30 <= io_commitPhys_0;
if (_GEN_3 & (&io_commitRd_1))
if (_GEN_64)
committed_31 <= io_commitPhys_1;
else if (_GEN_1 & (&io_commitRd_0))
else if (_GEN_31)
committed_31 <= io_commitPhys_0;
end
end // always @(posedge)
assign io_prs1_0 = _GEN[io_rs1_0];
assign io_prs1_1 = slot0Writes & io_rd_0 == io_rs1_1 ? io_newPhys_0 : _GEN[io_rs1_1];
assign io_prs2_0 = _GEN[io_rs2_0];
assign io_prs2_1 = slot0Writes & io_rd_0 == io_rs2_1 ? io_newPhys_0 : _GEN[io_rs2_1];
assign io_oldPrd_0 = _GEN[io_rd_0];
assign io_oldPrd_1 = slot0Writes & io_rd_0 == io_rd_1 ? io_newPhys_0 : _GEN[io_rd_1];
assign io_committedPhys_0 = committed_0;
assign io_committedPhys_1 = committed_1;
assign io_committedPhys_2 = committed_2;
assign io_committedPhys_3 = committed_3;
assign io_committedPhys_4 = committed_4;
assign io_committedPhys_5 = committed_5;
assign io_committedPhys_6 = committed_6;
assign io_committedPhys_7 = committed_7;
assign io_committedPhys_8 = committed_8;
assign io_committedPhys_9 = committed_9;
assign io_committedPhys_10 = committed_10;
assign io_committedPhys_11 = committed_11;
assign io_committedPhys_12 = committed_12;
assign io_committedPhys_13 = committed_13;
assign io_committedPhys_14 = committed_14;
assign io_committedPhys_15 = committed_15;
assign io_committedPhys_16 = committed_16;
assign io_committedPhys_17 = committed_17;
assign io_committedPhys_18 = committed_18;
assign io_committedPhys_19 = committed_19;
assign io_committedPhys_20 = committed_20;
assign io_committedPhys_21 = committed_21;
assign io_committedPhys_22 = committed_22;
assign io_committedPhys_23 = committed_23;
assign io_committedPhys_24 = committed_24;
assign io_committedPhys_25 = committed_25;
assign io_committedPhys_26 = committed_26;
assign io_committedPhys_27 = committed_27;
assign io_committedPhys_28 = committed_28;
assign io_committedPhys_29 = committed_29;
assign io_committedPhys_30 = committed_30;
assign io_committedPhys_31 = committed_31;
assign io_prs1_0 = _GEN_65[io_rs1_0];
assign io_prs1_1 = slot0Writes & io_rd_0 == io_rs1_1 ? io_newPhys_0 : _GEN_65[io_rs1_1];
assign io_prs2_0 = _GEN_65[io_rs2_0];
assign io_prs2_1 = slot0Writes & io_rd_0 == io_rs2_1 ? io_newPhys_0 : _GEN_65[io_rs2_1];
assign io_oldPrd_0 = _GEN_65[io_rd_0];
assign io_oldPrd_1 = slot0Writes & io_rd_0 == io_rd_1 ? io_newPhys_0 : _GEN_65[io_rd_1];
assign io_committedPhys_0 = committedNext_0;
assign io_committedPhys_1 = committedNext_1;
assign io_committedPhys_2 = committedNext_2;
assign io_committedPhys_3 = committedNext_3;
assign io_committedPhys_4 = committedNext_4;
assign io_committedPhys_5 = committedNext_5;
assign io_committedPhys_6 = committedNext_6;
assign io_committedPhys_7 = committedNext_7;
assign io_committedPhys_8 = committedNext_8;
assign io_committedPhys_9 = committedNext_9;
assign io_committedPhys_10 = committedNext_10;
assign io_committedPhys_11 = committedNext_11;
assign io_committedPhys_12 = committedNext_12;
assign io_committedPhys_13 = committedNext_13;
assign io_committedPhys_14 = committedNext_14;
assign io_committedPhys_15 = committedNext_15;
assign io_committedPhys_16 = committedNext_16;
assign io_committedPhys_17 = committedNext_17;
assign io_committedPhys_18 = committedNext_18;
assign io_committedPhys_19 = committedNext_19;
assign io_committedPhys_20 = committedNext_20;
assign io_committedPhys_21 = committedNext_21;
assign io_committedPhys_22 = committedNext_22;
assign io_committedPhys_23 = committedNext_23;
assign io_committedPhys_24 = committedNext_24;
assign io_committedPhys_25 = committedNext_25;
assign io_committedPhys_26 = committedNext_26;
assign io_committedPhys_27 = committedNext_27;
assign io_committedPhys_28 = committedNext_28;
assign io_committedPhys_29 = committedNext_29;
assign io_committedPhys_30 = committedNext_30;
assign io_committedPhys_31 = committedNext_31;
endmodule

1098
generated-ooo/ReservationStation.sv
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1950
generated-ooo/StoreQueue.sv
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