Initial Chisel core implementation

src/main/scala/frontend/RAS.scala

@@ -0,0 +1,31 @@
+import chisel3._
+import chisel3.util._
+
+class RAS(p: CoreParams = CoreParams()) extends Module {
+  private val ptrBits = log2Ceil(p.rasEntries)
+
+  val io = IO(new Bundle {
+    val push = Input(Bool())
+    val pop = Input(Bool())
+    val pushAddr = Input(UInt(p.xlen.W))
+    val top = Output(UInt(p.xlen.W))
+    val empty = Output(Bool())
+  })
+
+  val stack = Reg(Vec(p.rasEntries, UInt(p.xlen.W)))
+  val sp = RegInit(0.U(ptrBits.W))
+  val count = RegInit(0.U(log2Ceil(p.rasEntries + 1).W))
+
+  io.empty := count === 0.U
+  io.top := stack(Mux(sp === 0.U, (p.rasEntries - 1).U, sp - 1.U))
+
+  when(io.push) {
+    stack(sp) := io.pushAddr
+    sp := Mux(sp === (p.rasEntries - 1).U, 0.U, sp + 1.U)
+    when(count =/= p.rasEntries.U) { count := count + 1.U }
+  }.elsewhen(io.pop && count =/= 0.U) {
+    sp := Mux(sp === 0.U, (p.rasEntries - 1).U, sp - 1.U)
+    count := count - 1.U
+  }
+}
+