32 lines
881 B
Scala
32 lines
881 B
Scala
import chisel3._
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import chisel3.util._
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class RAS(p: CoreParams = CoreParams()) extends Module {
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private val ptrBits = log2Ceil(p.rasEntries)
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val io = IO(new Bundle {
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val push = Input(Bool())
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val pop = Input(Bool())
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val pushAddr = Input(UInt(p.xlen.W))
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val top = Output(UInt(p.xlen.W))
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val empty = Output(Bool())
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})
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val stack = Reg(Vec(p.rasEntries, UInt(p.xlen.W)))
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val sp = RegInit(0.U(ptrBits.W))
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val count = RegInit(0.U(log2Ceil(p.rasEntries + 1).W))
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io.empty := count === 0.U
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io.top := stack(Mux(sp === 0.U, (p.rasEntries - 1).U, sp - 1.U))
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when(io.push) {
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stack(sp) := io.pushAddr
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sp := Mux(sp === (p.rasEntries - 1).U, 0.U, sp + 1.U)
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when(count =/= p.rasEntries.U) { count := count + 1.U }
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}.elsewhen(io.pop && count =/= 0.U) {
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sp := Mux(sp === 0.U, (p.rasEntries - 1).U, sp - 1.U)
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count := count - 1.U
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}
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}
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