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[backend]适配SLL、SRL指令

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This commit is contained in:
Lixuanwang
2025-08-18 23:49:40 +08:00
parent 094b4c7c39
commit d7bf4b061f
3 changed files with 28 additions and 12 deletions
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16
src/backend/RISCv64/RISCv64Backend.cpp
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@@ -208,12 +208,12 @@ std::string RISCv64CodeGen::function_gen(Function* func) {
std::stringstream ss_after_isel; std::stringstream ss_after_isel;
RISCv64AsmPrinter printer_isel(mfunc.get()); RISCv64AsmPrinter printer_isel(mfunc.get());
printer_isel.run(ss_after_isel, true); printer_isel.run(ss_after_isel, true);
DEBUG = 1;
if (DEBUG) { if (DEBUG) {
std::cerr << "====== Intermediate Representation after Instruction Selection ======\n" std::cerr << "====== Intermediate Representation after Instruction Selection ======\n"
<< ss_after_isel.str(); << ss_after_isel.str();
} }
DEBUG = 0;
// 阶段 2: 消除帧索引 (展开伪指令，计算局部变量偏移) // 阶段 2: 消除帧索引 (展开伪指令，计算局部变量偏移)
EliminateFrameIndicesPass efi_pass; EliminateFrameIndicesPass efi_pass;
efi_pass.runOnMachineFunction(mfunc.get()); efi_pass.runOnMachineFunction(mfunc.get());
@@ -231,9 +231,9 @@ std::string RISCv64CodeGen::function_gen(Function* func) {
DivStrengthReduction div_strength_reduction; DivStrengthReduction div_strength_reduction;
div_strength_reduction.runOnMachineFunction(mfunc.get()); div_strength_reduction.runOnMachineFunction(mfunc.get());
// 阶段 2.2: 指令调度 (Instruction Scheduling) // // 阶段 2.2: 指令调度 (Instruction Scheduling)
PreRA_Scheduler scheduler; // PreRA_Scheduler scheduler;
scheduler.runOnMachineFunction(mfunc.get()); // scheduler.runOnMachineFunction(mfunc.get());
// 阶段 3: 物理寄存器分配 (Register Allocation) // 阶段 3: 物理寄存器分配 (Register Allocation)
bool allocation_succeeded = false; bool allocation_succeeded = false;
@@ -345,9 +345,9 @@ std::string RISCv64CodeGen::function_gen(Function* func) {
PeepholeOptimizer peephole; PeepholeOptimizer peephole;
peephole.runOnMachineFunction(mfunc.get()); peephole.runOnMachineFunction(mfunc.get());
// 阶段 5: 局部指令调度 (Local Scheduling) // // 阶段 5: 局部指令调度 (Local Scheduling)
PostRA_Scheduler local_scheduler; // PostRA_Scheduler local_scheduler;
local_scheduler.runOnMachineFunction(mfunc.get()); // local_scheduler.runOnMachineFunction(mfunc.get());
// 阶段 3.2: 插入序言和尾声 // 阶段 3.2: 插入序言和尾声
PrologueEpilogueInsertionPass pei_pass; PrologueEpilogueInsertionPass pei_pass;

18
src/backend/RISCv64/RISCv64ISel.cpp
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@@ -526,6 +526,22 @@ void RISCv64ISel::selectNode(DAGNode* node) {
CurMBB->addInstruction(std::move(instr)); CurMBB->addInstruction(std::move(instr));
break; break;
} }
case BinaryInst::kSll: { // 逻辑左移
auto instr = std::make_unique<MachineInstr>(RVOpcodes::SLLW);
instr->addOperand(std::make_unique<RegOperand>(dest_vreg));
instr->addOperand(std::make_unique<RegOperand>(lhs_vreg));
instr->addOperand(std::make_unique<RegOperand>(rhs_vreg));
CurMBB->addInstruction(std::move(instr));
break;
}
case BinaryInst::kSrl: { // 逻辑右移
auto instr = std::make_unique<MachineInstr>(RVOpcodes::SRLW);
instr->addOperand(std::make_unique<RegOperand>(dest_vreg));
instr->addOperand(std::make_unique<RegOperand>(lhs_vreg));
instr->addOperand(std::make_unique<RegOperand>(rhs_vreg));
CurMBB->addInstruction(std::move(instr));
break;
}
case BinaryInst::kICmpEQ: { // 等于 (a == b) -> (subw; seqz) case BinaryInst::kICmpEQ: { // 等于 (a == b) -> (subw; seqz)
auto sub = std::make_unique<MachineInstr>(RVOpcodes::SUBW); auto sub = std::make_unique<MachineInstr>(RVOpcodes::SUBW);
sub->addOperand(std::make_unique<RegOperand>(dest_vreg)); sub->addOperand(std::make_unique<RegOperand>(dest_vreg));
@@ -582,7 +598,7 @@ void RISCv64ISel::selectNode(DAGNode* node) {
CurMBB->addInstruction(std::move(xori)); CurMBB->addInstruction(std::move(xori));
break; break;
} }
case BinaryInst::kICmpGE: { // 大于等于 (a >= b) -> !(a < b) -> (slt; xori) case BinaryInst::kICmpGE: { // 大于等于 (a >= b) -> !(a < b) -> (slt; xori)
auto slt = std::make_unique<MachineInstr>(RVOpcodes::SLT); auto slt = std::make_unique<MachineInstr>(RVOpcodes::SLT);
slt->addOperand(std::make_unique<RegOperand>(dest_vreg)); slt->addOperand(std::make_unique<RegOperand>(dest_vreg));
slt->addOperand(std::make_unique<RegOperand>(lhs_vreg)); slt->addOperand(std::make_unique<RegOperand>(lhs_vreg));

6
src/midend/Pass/Pass.cpp
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@@ -192,9 +192,9 @@ void PassManager::runOptimizationPipeline(Module* moduleIR, IRBuilder* builderIR
printPasses(); printPasses();
} }
// this->clearPasses(); this->clearPasses();
// this->addPass(&Reg2Mem::ID); this->addPass(&Reg2Mem::ID);
// this->run(); this->run();
if(DEBUG) { if(DEBUG) {
std::cout << "=== IR After Reg2Mem Optimizations ===\n"; std::cout << "=== IR After Reg2Mem Optimizations ===\n";