diff --git a/src/backend/RISCv64/RISCv64Backend.cpp b/src/backend/RISCv64/RISCv64Backend.cpp index f2b6562..6be37fc 100644 --- a/src/backend/RISCv64/RISCv64Backend.cpp +++ b/src/backend/RISCv64/RISCv64Backend.cpp @@ -208,12 +208,12 @@ std::string RISCv64CodeGen::function_gen(Function* func) { std::stringstream ss_after_isel; RISCv64AsmPrinter printer_isel(mfunc.get()); printer_isel.run(ss_after_isel, true); - + DEBUG = 1; if (DEBUG) { std::cerr << "====== Intermediate Representation after Instruction Selection ======\n" << ss_after_isel.str(); } - + DEBUG = 0; // 阶段 2: 消除帧索引 (展开伪指令,计算局部变量偏移) EliminateFrameIndicesPass efi_pass; efi_pass.runOnMachineFunction(mfunc.get()); @@ -231,9 +231,9 @@ std::string RISCv64CodeGen::function_gen(Function* func) { DivStrengthReduction div_strength_reduction; div_strength_reduction.runOnMachineFunction(mfunc.get()); - // 阶段 2.2: 指令调度 (Instruction Scheduling) - PreRA_Scheduler scheduler; - scheduler.runOnMachineFunction(mfunc.get()); + // // 阶段 2.2: 指令调度 (Instruction Scheduling) + // PreRA_Scheduler scheduler; + // scheduler.runOnMachineFunction(mfunc.get()); // 阶段 3: 物理寄存器分配 (Register Allocation) bool allocation_succeeded = false; @@ -345,9 +345,9 @@ std::string RISCv64CodeGen::function_gen(Function* func) { PeepholeOptimizer peephole; peephole.runOnMachineFunction(mfunc.get()); - // 阶段 5: 局部指令调度 (Local Scheduling) - PostRA_Scheduler local_scheduler; - local_scheduler.runOnMachineFunction(mfunc.get()); + // // 阶段 5: 局部指令调度 (Local Scheduling) + // PostRA_Scheduler local_scheduler; + // local_scheduler.runOnMachineFunction(mfunc.get()); // 阶段 3.2: 插入序言和尾声 PrologueEpilogueInsertionPass pei_pass; diff --git a/src/backend/RISCv64/RISCv64ISel.cpp b/src/backend/RISCv64/RISCv64ISel.cpp index 176739b..a0ad2f1 100644 --- a/src/backend/RISCv64/RISCv64ISel.cpp +++ b/src/backend/RISCv64/RISCv64ISel.cpp @@ -526,6 +526,22 @@ void RISCv64ISel::selectNode(DAGNode* node) { CurMBB->addInstruction(std::move(instr)); break; } + case BinaryInst::kSll: { // 逻辑左移 + auto instr = std::make_unique(RVOpcodes::SLLW); + instr->addOperand(std::make_unique(dest_vreg)); + instr->addOperand(std::make_unique(lhs_vreg)); + instr->addOperand(std::make_unique(rhs_vreg)); + CurMBB->addInstruction(std::move(instr)); + break; + } + case BinaryInst::kSrl: { // 逻辑右移 + auto instr = std::make_unique(RVOpcodes::SRLW); + instr->addOperand(std::make_unique(dest_vreg)); + instr->addOperand(std::make_unique(lhs_vreg)); + instr->addOperand(std::make_unique(rhs_vreg)); + CurMBB->addInstruction(std::move(instr)); + break; + } case BinaryInst::kICmpEQ: { // 等于 (a == b) -> (subw; seqz) auto sub = std::make_unique(RVOpcodes::SUBW); sub->addOperand(std::make_unique(dest_vreg)); @@ -582,7 +598,7 @@ void RISCv64ISel::selectNode(DAGNode* node) { CurMBB->addInstruction(std::move(xori)); break; } - case BinaryInst::kICmpGE: { // 大于等于 (a >= b) -> !(a < b) -> (slt; xori) + case BinaryInst::kICmpGE: { // 大于等于 (a >= b) -> !(a < b) -> (slt; xori) auto slt = std::make_unique(RVOpcodes::SLT); slt->addOperand(std::make_unique(dest_vreg)); slt->addOperand(std::make_unique(lhs_vreg)); diff --git a/src/midend/Pass/Pass.cpp b/src/midend/Pass/Pass.cpp index aee29b0..b8c386d 100644 --- a/src/midend/Pass/Pass.cpp +++ b/src/midend/Pass/Pass.cpp @@ -192,9 +192,9 @@ void PassManager::runOptimizationPipeline(Module* moduleIR, IRBuilder* builderIR printPasses(); } - // this->clearPasses(); - // this->addPass(&Reg2Mem::ID); - // this->run(); + this->clearPasses(); + this->addPass(&Reg2Mem::ID); + this->run(); if(DEBUG) { std::cout << "=== IR After Reg2Mem Optimizations ===\n";