SystemVerilog Module Complete

.gitignore

@@ -4,7 +4,10 @@
 .history
 .metals
 .bloop
+.scalafmt.conf
 *.code-workspace
+target/*
+.vscode
 
 # virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
 hs_err_pid*

Core.sv

@@ -0,0 +1,427 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2024/12/28 11:25:38
+// Design Name:
+// Module Name: Core
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module Core(
+        input         clock,
+        reset,
+        output [31:0] io_imem_addr,
+        input  [31:0] io_imem_inst,
+        output [31:0] io_dmem_addr,
+        input  [31:0] io_dmem_rdata,
+        output        io_dmem_wen,
+        output [31:0] io_dmem_wdata,
+        output [3:0]  io_anodes,
+        output [6:0]  io_segments,
+        output        io_exit
+    );
+
+    wire        exe_jmp_flg;
+    wire        exe_br_flg;
+    wire [31:0] _regfile_ext_R0_data;
+    wire [31:0] _regfile_ext_R1_data;
+    reg  [31:0] id_reg_pc;
+    reg  [31:0] id_reg_inst;
+    reg  [31:0] exe_reg_pc;
+    reg  [4:0]  exe_reg_wb_addr;
+    reg  [31:0] exe_reg_op1_data;
+    reg  [31:0] exe_reg_op2_data;
+    reg  [31:0] exe_reg_rt_data;
+    reg  [4:0]  exe_reg_exe_fun;
+    reg  [1:0]  exe_reg_mem_wen;
+    reg  [1:0]  exe_reg_rf_wen;
+    reg  [2:0]  exe_reg_wb_sel;
+    reg  [31:0] exe_reg_imm_i_sext;
+    reg  [31:0] mem_reg_pc;
+    reg  [4:0]  mem_reg_wb_addr;
+    reg  [31:0] mem_reg_rt_data;
+    reg  [1:0]  mem_reg_mem_wen;
+    reg  [1:0]  mem_reg_rf_wen;
+    reg  [2:0]  mem_reg_wb_sel;
+    reg  [31:0] mem_reg_alu_out;
+    reg  [4:0]  wb_reg_wb_addr;
+    reg  [1:0]  wb_reg_rf_wen;
+    reg  [31:0] wb_reg_wb_data;
+    reg  [31:0] if_reg_pc;
+    wire        _id_inst_T = exe_br_flg | exe_jmp_flg;
+    wire        _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1;
+    wire        stall_flg =
+                _id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr
+                | _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
+    wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst;
+    wire        _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1;
+    wire        _exe_alu_out_T = exe_reg_exe_fun == 5'h1;
+    wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data;
+    wire        _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2;
+    wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data;
+    wire        _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3;
+    wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data;
+    wire        _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4;
+    wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data;
+    wire        _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5;
+    wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data;
+    wire        _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6;
+    wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
+    wire        _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7;
+    wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]};
+    wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN;
+    wire        _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8;
+    wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN);
+    wire        _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9;
+    wire        _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD;
+    wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0;
+    wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)};
+    wire [31:0] exe_alu_out =
+         _exe_alu_out_T
+         ? _exe_alu_out_T_1
+         : _exe_alu_out_T_3
+         ? _exe_alu_out_T_4
+         : _exe_alu_out_T_6
+         ? _exe_alu_out_T_7
+         : _exe_alu_out_T_8
+         ? _exe_alu_out_T_9
+         : _exe_alu_out_T_10
+         ? _exe_alu_out_T_11
+         : _exe_alu_out_T_12
+         ? _exe_alu_out_T_14[31:0]
+         : _exe_alu_out_T_16
+         ? _exe_alu_out_T_18
+         : _exe_alu_out_T_19
+         ? _exe_alu_out_T_22
+         : _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29;
+    assign exe_br_flg =
+           exe_reg_exe_fun == 5'hB
+           ? exe_reg_op1_data == exe_reg_op2_data
+           : exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
+    assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
+    wire [31:0] mem_wb_data =
+         mem_reg_wb_sel == 3'h2
+         ? io_dmem_rdata
+         : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
+    always @(posedge clock) begin
+        if (reset) begin
+            id_reg_pc <= 32'h0;
+            id_reg_inst <= 32'h0;
+            exe_reg_pc <= 32'h0;
+            exe_reg_wb_addr <= 5'h0;
+            exe_reg_op1_data <= 32'h0;
+            exe_reg_op2_data <= 32'h0;
+            exe_reg_rt_data <= 32'h0;
+            exe_reg_exe_fun <= 5'h0;
+            exe_reg_mem_wen <= 2'h0;
+            exe_reg_rf_wen <= 2'h0;
+            exe_reg_wb_sel <= 3'h0;
+            exe_reg_imm_i_sext <= 32'h0;
+            mem_reg_pc <= 32'h0;
+            mem_reg_wb_addr <= 5'h0;
+            mem_reg_rt_data <= 32'h0;
+            mem_reg_mem_wen <= 2'h0;
+            mem_reg_rf_wen <= 2'h0;
+            mem_reg_wb_sel <= 3'h0;
+            mem_reg_alu_out <= 32'h0;
+            wb_reg_wb_addr <= 5'h0;
+            wb_reg_rf_wen <= 2'h0;
+            wb_reg_wb_data <= 32'h0;
+            if_reg_pc <= 32'h0;
+        end
+        else begin
+            automatic logic        _id_rt_data_T_5;
+            automatic logic        _id_rt_data_T;
+            automatic logic        _id_rt_data_T_3;
+            automatic logic        _id_rt_data_T_6;
+            automatic logic        _id_rt_data_T_9;
+            automatic logic [31:0] id_imm_i_sext;
+            automatic logic        _csignals_T_1 = id_inst[31:26] == 6'h23;
+            automatic logic        _csignals_T_3;
+            automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]};
+            automatic logic        _csignals_T_5 = _GEN_1 == 12'h20;
+            automatic logic        _csignals_T_7 = id_inst[31:26] == 6'h8;
+            automatic logic        _csignals_T_9;
+            automatic logic        _csignals_T_11;
+            automatic logic        _csignals_T_13;
+            automatic logic        _csignals_T_15;
+            automatic logic        _csignals_T_17;
+            automatic logic        _csignals_T_19;
+            automatic logic        _csignals_T_21;
+            automatic logic        _csignals_T_23;
+            automatic logic        _csignals_T_25;
+            automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]};
+            automatic logic        _csignals_T_27;
+            automatic logic        _csignals_T_29;
+            automatic logic        _csignals_T_31;
+            automatic logic        _csignals_T_33;
+            automatic logic        _csignals_T_35;
+            automatic logic        _GEN_3;
+            automatic logic        _GEN_4;
+            automatic logic [1:0]  csignals_1;
+            automatic logic [2:0]  csignals_2;
+            automatic logic        _GEN_5;
+            automatic logic        _GEN_6;
+            _id_rt_data_T_5 = mem_reg_rf_wen == 2'h1;
+            _id_rt_data_T = id_inst[20:16] == 5'h0;
+            _id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
+            _id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
+            _id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
+            id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
+            _csignals_T_3 = id_inst[31:26] == 6'h2B;
+            _csignals_T_9 = _GEN_1 == 12'h22;
+            _csignals_T_11 = _GEN_1 == 12'h24;
+            _csignals_T_13 = _GEN_1 == 12'h25;
+            _csignals_T_15 = _GEN_1 == 12'h26;
+            _csignals_T_17 = id_inst[31:26] == 6'hC;
+            _csignals_T_19 = id_inst[31:26] == 6'hD;
+            _csignals_T_21 = _GEN_1 == 12'h2A;
+            _csignals_T_23 = id_inst[31:26] == 6'h4;
+            _csignals_T_25 = id_inst[31:26] == 6'h5;
+            _csignals_T_27 = _GEN_2 == 17'h0;
+            _csignals_T_29 = _GEN_2 == 17'h2;
+            _csignals_T_31 = _GEN_2 == 17'h3;
+            _csignals_T_33 = id_inst[31:26] == 6'h3;
+            _csignals_T_35 = _GEN_1 == 12'h8;
+            _GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
+            _GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
+            csignals_1 =
+                _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
+                | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
+                | _csignals_T_19 | _GEN_4 | ~_csignals_T_33
+                ? 2'h1
+                : 2'h2;
+            csignals_2 =
+                _csignals_T_1 | _csignals_T_3
+                ? 3'h2
+                : _csignals_T_5
+                ? 3'h1
+                : _csignals_T_7
+                ? 3'h2
+                : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
+                ? 3'h1
+                : _csignals_T_17 | _csignals_T_19
+                ? 3'h2
+                : _GEN_4
+                ? 3'h1
+                : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
+            _GEN_5 = _csignals_T_23 | _csignals_T_25;
+            _GEN_6 =
+                _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+                | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
+            if (~stall_flg)
+                id_reg_pc <= if_reg_pc;
+            if (_id_inst_T)
+                id_reg_inst <= 32'h20000000;
+            else if (~stall_flg)
+                id_reg_inst <= io_imem_inst;
+            exe_reg_pc <= id_reg_pc;
+            if ((_csignals_T_1
+                    ? 3'h2
+                    : _csignals_T_3
+                    ? 3'h0
+                    : _GEN_6
+                    ? 3'h1
+                    : _GEN_5
+                    ? 3'h0
+                    : _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
+                    & id_inst[31:26] == 6'h0)
+                exe_reg_wb_addr <= id_inst[15:11];
+            else if (id_inst[31:26] == 6'h3)
+                exe_reg_wb_addr <= 5'h1F;
+            else
+                exe_reg_wb_addr <= id_inst[20:16];
+            if (csignals_1 == 2'h1) begin
+                if (id_inst[25:21] == 5'h0)
+                    exe_reg_op1_data <= 32'h0;
+                else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
+                    if (_exe_alu_out_T)
+                        exe_reg_op1_data <= _exe_alu_out_T_1;
+                    else if (_exe_alu_out_T_3)
+                        exe_reg_op1_data <= _exe_alu_out_T_4;
+                    else if (_exe_alu_out_T_6)
+                        exe_reg_op1_data <= _exe_alu_out_T_7;
+                    else if (_exe_alu_out_T_8)
+                        exe_reg_op1_data <= _exe_alu_out_T_9;
+                    else if (_exe_alu_out_T_10)
+                        exe_reg_op1_data <= _exe_alu_out_T_11;
+                    else if (_exe_alu_out_T_12)
+                        exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
+                    else if (_exe_alu_out_T_16)
+                        exe_reg_op1_data <= _exe_alu_out_T_18;
+                    else if (_exe_alu_out_T_19)
+                        exe_reg_op1_data <= _exe_alu_out_T_22;
+                    else if (_exe_alu_out_T_24)
+                        exe_reg_op1_data <= _GEN_0;
+                    else if (~_exe_alu_out_T_28)
+                        exe_reg_op1_data <= 32'h0;
+                end
+                else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
+                    exe_reg_op1_data <= mem_wb_data;
+                else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
+                    exe_reg_op1_data <= wb_reg_wb_data;
+                else
+                    exe_reg_op1_data <= _regfile_ext_R1_data;
+            end
+            else if (csignals_1 == 2'h2)
+                exe_reg_op1_data <= id_reg_pc;
+            else
+                exe_reg_op1_data <= 32'h0;
+            if (csignals_2 == 3'h1) begin
+                if (_id_rt_data_T)
+                    exe_reg_op2_data <= 32'h0;
+                else if (_id_rt_data_T_3) begin
+                    if (_exe_alu_out_T)
+                        exe_reg_op2_data <= _exe_alu_out_T_1;
+                    else if (_exe_alu_out_T_3)
+                        exe_reg_op2_data <= _exe_alu_out_T_4;
+                    else if (_exe_alu_out_T_6)
+                        exe_reg_op2_data <= _exe_alu_out_T_7;
+                    else if (_exe_alu_out_T_8)
+                        exe_reg_op2_data <= _exe_alu_out_T_9;
+                    else if (_exe_alu_out_T_10)
+                        exe_reg_op2_data <= _exe_alu_out_T_11;
+                    else if (_exe_alu_out_T_12)
+                        exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
+                    else if (_exe_alu_out_T_16)
+                        exe_reg_op2_data <= _exe_alu_out_T_18;
+                    else if (_exe_alu_out_T_19)
+                        exe_reg_op2_data <= _exe_alu_out_T_22;
+                    else if (_exe_alu_out_T_24)
+                        exe_reg_op2_data <= _GEN_0;
+                    else
+                        exe_reg_op2_data <= _exe_alu_out_T_29;
+                end
+                else if (_id_rt_data_T_6)
+                    exe_reg_op2_data <= mem_wb_data;
+                else if (_id_rt_data_T_9)
+                    exe_reg_op2_data <= wb_reg_wb_data;
+                else
+                    exe_reg_op2_data <= _regfile_ext_R0_data;
+            end
+            else if (csignals_2 == 3'h2)
+                exe_reg_op2_data <= id_imm_i_sext;
+            else if (csignals_2 == 3'h4)
+                exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
+            else
+                exe_reg_op2_data <= 32'h0;
+            exe_reg_rt_data <=
+                            _id_rt_data_T
+                            ? 32'h0
+                            : _id_rt_data_T_3
+                            ? exe_alu_out
+                            : _id_rt_data_T_6
+                            ? mem_wb_data
+                            : _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
+            if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
+                exe_reg_exe_fun <= 5'h1;
+            else if (_csignals_T_9)
+                exe_reg_exe_fun <= 5'h2;
+            else if (_csignals_T_11)
+                exe_reg_exe_fun <= 5'h3;
+            else if (_csignals_T_13)
+                exe_reg_exe_fun <= 5'h4;
+            else if (_csignals_T_15)
+                exe_reg_exe_fun <= 5'h5;
+            else if (_csignals_T_17)
+                exe_reg_exe_fun <= 5'h3;
+            else if (_csignals_T_19)
+                exe_reg_exe_fun <= 5'h4;
+            else if (_csignals_T_21)
+                exe_reg_exe_fun <= 5'h9;
+            else if (_csignals_T_23)
+                exe_reg_exe_fun <= 5'hB;
+            else if (_csignals_T_25)
+                exe_reg_exe_fun <= 5'hC;
+            else if (_csignals_T_27)
+                exe_reg_exe_fun <= 5'h6;
+            else if (_csignals_T_29)
+                exe_reg_exe_fun <= 5'h7;
+            else if (_csignals_T_31)
+                exe_reg_exe_fun <= 5'h8;
+            else if (_csignals_T_33)
+                exe_reg_exe_fun <= 5'h1;
+            else if (_csignals_T_35)
+                exe_reg_exe_fun <= 5'hD;
+            else
+                exe_reg_exe_fun <= 5'h0;
+            exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
+            if (_csignals_T_1) begin
+                exe_reg_rf_wen <= 2'h1;
+                exe_reg_wb_sel <= 3'h2;
+            end
+            else if (_csignals_T_3) begin
+                exe_reg_rf_wen <= 2'h0;
+                exe_reg_wb_sel <= 3'h0;
+            end
+            else if (_GEN_6) begin
+                exe_reg_rf_wen <= 2'h1;
+                exe_reg_wb_sel <= 3'h1;
+            end
+            else if (_GEN_5) begin
+                exe_reg_rf_wen <= 2'h0;
+                exe_reg_wb_sel <= 3'h0;
+            end
+            else begin
+                exe_reg_rf_wen <=
+                               {1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
+                if (_GEN_3)
+                    exe_reg_wb_sel <= 3'h1;
+                else if (_csignals_T_33)
+                    exe_reg_wb_sel <= 3'h3;
+                else
+                    exe_reg_wb_sel <= 3'h0;
+            end
+            exe_reg_imm_i_sext <= id_imm_i_sext;
+            mem_reg_pc <= exe_reg_pc;
+            mem_reg_wb_addr <= exe_reg_wb_addr;
+            mem_reg_rt_data <= exe_reg_rt_data;
+            mem_reg_mem_wen <= exe_reg_mem_wen;
+            mem_reg_rf_wen <= exe_reg_rf_wen;
+            mem_reg_wb_sel <= exe_reg_wb_sel;
+            mem_reg_alu_out <= exe_alu_out;
+            wb_reg_wb_addr <= mem_reg_wb_addr;
+            wb_reg_rf_wen <= mem_reg_rf_wen;
+            wb_reg_wb_data <= mem_wb_data;
+            if (exe_br_flg)
+                if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
+            else if (exe_jmp_flg)
+                if_reg_pc <= exe_alu_out;
+            else if (~stall_flg)
+                if_reg_pc <= if_reg_pc + 32'h4;
+        end
+    end // always @(posedge)
+    regfile_32x32 regfile_ext (
+                      .R0_addr (id_inst[20:16]),
+                      .R0_en   (1'h1),
+                      .R0_clk  (clock),
+                      .R0_data (_regfile_ext_R0_data),
+                      .R1_addr (id_inst[25:21]),
+                      .R1_en   (1'h1),
+                      .R1_clk  (clock),
+                      .R1_data (_regfile_ext_R1_data),
+                      .W0_addr (wb_reg_wb_addr),
+                      .W0_en   (_id_rt_data_T_8 & (|wb_reg_wb_addr)),
+                      .W0_clk  (clock),
+                      .io_anodes (io_anodes),
+                      .io_segments (io_segments),
+                      .W0_data (wb_reg_wb_data)
+                  );
+    assign io_imem_addr = if_reg_pc;
+    assign io_dmem_addr = mem_reg_alu_out;
+    assign io_dmem_wen = mem_reg_mem_wen[0];
+    assign io_dmem_wdata = mem_reg_rt_data;
+    assign io_exit = id_reg_inst == 32'h114514;
+endmodule

Display.sv

@@ -0,0 +1,67 @@
+module DynamicDisplay(
+        input        clock,
+        reset,
+        input  [31:0] reg_result,
+        output [3:0] io_anodes,
+        output [6:0] io_segments
+    );
+
+    reg [6:0] digit_segments [0:9];
+    initial begin
+        digit_segments[0] = 7'b0000001;
+        digit_segments[1] = 7'b1001111;
+        digit_segments[2] = 7'b0010010;
+        digit_segments[3] = 7'b0000110;
+        digit_segments[4] = 7'b1001100;
+        digit_segments[5] = 7'b0100100;
+        digit_segments[6] = 7'b0100000;
+        digit_segments[7] = 7'b0001111;
+        digit_segments[8] = 7'b0000000;
+        digit_segments[9] = 7'b0000100;
+    end
+
+    reg [3:0] anode_select [0:3];
+    initial begin
+        anode_select[0] = 4'b1110;
+        anode_select[1] = 4'b1101;
+        anode_select[2] = 4'b1011;
+        anode_select[3] = 4'b0111;
+    end
+
+    // 扫描计数器和时钟分频
+    reg [15:0] clkDiv;          // 分频计数器
+    reg [1:0]  scanCounter;     // 扫描计数器
+    wire       clk1kHz = (clkDiv == 16'd50_000);
+
+    always @(posedge clock or posedge reset) begin
+        if (reset) begin
+            clkDiv <= 16'd0;
+            scanCounter <= 2'd0;
+        end
+        else begin
+            if (clk1kHz) begin
+                clkDiv <= 16'd0;
+                scanCounter <= scanCounter + 2'd1;
+            end
+            else begin
+                clkDiv <= clkDiv + 16'd1;
+            end
+        end
+    end
+
+    reg [3:0] digit_value;
+    always @(*) begin
+        case (scanCounter)
+            2'b11: digit_value = reg_result / 1000;         // 千位
+            2'b10: digit_value = (reg_result / 100) % 10;  // 百位
+            2'b01: digit_value = (reg_result / 10) % 10;   // 十位
+            2'b00: digit_value = reg_result % 10;          // 个位
+            default:
+                digit_value = 4'd0;
+        endcase
+    end
+
+    assign io_segments = digit_segments[digit_value];
+    assign io_anodes = anode_select[scanCounter];
+
+endmodule

GCD.sv

@@ -1,27 +0,0 @@
-// Generated by CIRCT firtool-1.62.0
-module GCD(
-  input         clock,
-                reset,
-  input  [15:0] io_value1,
-                io_value2,
-  input         io_loadingValues,
-  output [15:0] io_outputGCD,
-  output        io_outputValid
-);
-
-  reg [15:0] x;
-  reg [15:0] y;
-  always @(posedge clock) begin
-    if (io_loadingValues) begin
-      x <= io_value1;
-      y <= io_value2;
-    end
-    else if (x > y)
-      x <= x - y;
-    else
-      y <= y - x;
-  end // always @(posedge)
-  assign io_outputGCD = x;
-  assign io_outputValid = y == 16'h0;
-endmodule
-

Memory.sv

@@ -0,0 +1,173 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2024/12/28 11:28:52
+// Design Name:
+// Module Name: Regfile
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mem_4096x8(
+        input  [11:0] R0_addr,
+        input         R0_en,
+        R0_clk,
+        output [7:0]  R0_data,
+        input  [11:0] R1_addr,
+        input         R1_en,
+        R1_clk,
+        output [7:0]  R1_data,
+        input  [11:0] R2_addr,
+        input         R2_en,
+        R2_clk,
+        output [7:0]  R2_data,
+        input  [11:0] R3_addr,
+        input         R3_en,
+        R3_clk,
+        output [7:0]  R3_data,
+        input  [11:0] R4_addr,
+        input         R4_en,
+        R4_clk,
+        output [7:0]  R4_data,
+        input  [11:0] R5_addr,
+        input         R5_en,
+        R5_clk,
+        output [7:0]  R5_data,
+        input  [11:0] R6_addr,
+        input         R6_en,
+        R6_clk,
+        output [7:0]  R6_data,
+        input  [11:0] R7_addr,
+        input         R7_en,
+        R7_clk,
+        output [7:0]  R7_data,
+        input  [11:0] W0_addr,
+        input         W0_en,
+        W0_clk,
+        input  [7:0]  W0_data,
+        input  [11:0] W1_addr,
+        input         W1_en,
+        W1_clk,
+        input  [7:0]  W1_data,
+        input  [11:0] W2_addr,
+        input         W2_en,
+        W2_clk,
+        input  [7:0]  W2_data,
+        input  [11:0] W3_addr,
+        input         W3_en,
+        W3_clk,
+        input  [7:0]  W3_data
+    );
+
+    reg [7:0] Memory[0:4095];
+    always @(posedge W0_clk) begin
+        if (W0_en & 1'h1)
+            Memory[W0_addr] <= W0_data;
+        if (W1_en & 1'h1)
+            Memory[W1_addr] <= W1_data;
+        if (W2_en & 1'h1)
+            Memory[W2_addr] <= W2_data;
+        if (W3_en & 1'h1)
+            Memory[W3_addr] <= W3_data;
+    end // always @(posedge)
+`ifdef ENABLE_INITIAL_MEM_
+    initial
+        $readmemh("src/hex/mem.hex", Memory);
+`endif // ENABLE_INITIAL_MEM_
+
+    assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
+    assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
+    assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
+    assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
+    assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
+    assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
+    assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
+    assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
+endmodule
+
+module Memory(
+        input         clock,
+        input  [31:0] io_imem_addr,
+        output [31:0] io_imem_inst,
+        input  [31:0] io_dmem_addr,
+        output [31:0] io_dmem_rdata,
+        input         io_dmem_wen,
+        input  [31:0] io_dmem_wdata
+    );
+
+    wire [7:0]  _mem_ext_R0_data;
+    wire [7:0]  _mem_ext_R1_data;
+    wire [7:0]  _mem_ext_R2_data;
+    wire [7:0]  _mem_ext_R3_data;
+    wire [7:0]  _mem_ext_R4_data;
+    wire [7:0]  _mem_ext_R5_data;
+    wire [7:0]  _mem_ext_R6_data;
+    wire [7:0]  _mem_ext_R7_data;
+    wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
+    wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
+    wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
+    mem_4096x8 mem_ext (
+                   .R0_addr (io_imem_addr[11:0]),
+                   .R0_en   (1'h1),
+                   .R0_clk  (clock),
+                   .R0_data (_mem_ext_R0_data),
+                   .R1_addr (io_imem_addr[11:0] + 12'h1),
+                   .R1_en   (1'h1),
+                   .R1_clk  (clock),
+                   .R1_data (_mem_ext_R1_data),
+                   .R2_addr (io_imem_addr[11:0] + 12'h2),
+                   .R2_en   (1'h1),
+                   .R2_clk  (clock),
+                   .R2_data (_mem_ext_R2_data),
+                   .R3_addr (io_imem_addr[11:0] + 12'h3),
+                   .R3_en   (1'h1),
+                   .R3_clk  (clock),
+                   .R3_data (_mem_ext_R3_data),
+                   .R4_addr (io_dmem_addr[11:0]),
+                   .R4_en   (1'h1),
+                   .R4_clk  (clock),
+                   .R4_data (_mem_ext_R4_data),
+                   .R5_addr (_io_dmem_rdata_T_6),
+                   .R5_en   (1'h1),
+                   .R5_clk  (clock),
+                   .R5_data (_mem_ext_R5_data),
+                   .R6_addr (_io_dmem_rdata_T_3),
+                   .R6_en   (1'h1),
+                   .R6_clk  (clock),
+                   .R6_data (_mem_ext_R6_data),
+                   .R7_addr (_io_dmem_rdata_T),
+                   .R7_en   (1'h1),
+                   .R7_clk  (clock),
+                   .R7_data (_mem_ext_R7_data),
+                   .W0_addr (_io_dmem_rdata_T),
+                   .W0_en   (io_dmem_wen),
+                   .W0_clk  (clock),
+                   .W0_data (io_dmem_wdata[31:24]),
+                   .W1_addr (_io_dmem_rdata_T_3),
+                   .W1_en   (io_dmem_wen),
+                   .W1_clk  (clock),
+                   .W1_data (io_dmem_wdata[23:16]),
+                   .W2_addr (_io_dmem_rdata_T_6),
+                   .W2_en   (io_dmem_wen),
+                   .W2_clk  (clock),
+                   .W2_data (io_dmem_wdata[15:8]),
+                   .W3_addr (io_dmem_addr[11:0]),
+                   .W3_en   (io_dmem_wen),
+                   .W3_clk  (clock),
+                   .W3_data (io_dmem_wdata[7:0])
+               );
+    assign io_imem_inst =
+           {_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
+    assign io_dmem_rdata =
+           {_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
+endmodule

Regfile.sv

@@ -0,0 +1,54 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2024/12/28 11:28:52
+// Design Name:
+// Module Name: Regfile
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module regfile_32x32(
+        input  [4:0]  R0_addr,
+        input         R0_en,
+        R0_clk,
+        output [31:0] R0_data,
+        input  [4:0]  R1_addr,
+        input         R1_en,
+        R1_clk,
+        output [31:0] R1_data,
+        input  [4:0]  W0_addr,
+        input         W0_en,
+        W0_clk,
+        output [3:0]  io_anodes,
+        output [6:0]  io_segments,
+        input  [31:0] W0_data
+    );
+
+    reg [31:0] Memory[0:31];
+    always @(posedge W0_clk) begin
+        if (W0_en & 1'h1)
+            Memory[W0_addr] <= W0_data;
+    end // always @(posedge)
+    assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
+    assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
+    wire [31:0] reg16_value = Memory[16];
+    DynamicDisplay display (
+                       .clock        (W0_clk),
+                       .reset        (1'b0),
+                       .reg_result   (reg16_value),
+                       .io_anodes    (io_anodes),
+                       .io_segments  (io_segments)
+                   );
+endmodule
+

Top.sv

@@ -0,0 +1,58 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2024/12/28 11:25:38
+// Design Name:
+// Module Name: Core
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module Top(
+        input  clock,
+        reset,
+        output io_exit,
+        output [3:0] io_anodes,
+        output [6:0] io_segments
+    );
+
+    wire [31:0] _memory_io_imem_inst;
+    wire [31:0] _memory_io_dmem_rdata;
+    wire [31:0] _core_io_imem_addr;
+    wire [31:0] _core_io_dmem_addr;
+    wire        _core_io_dmem_wen;
+    wire [31:0] _core_io_dmem_wdata;
+    Core core (
+             .clock         (clock),
+             .reset         (reset),
+             .io_imem_addr  (_core_io_imem_addr),
+             .io_imem_inst  (_memory_io_imem_inst),
+             .io_dmem_addr  (_core_io_dmem_addr),
+             .io_dmem_rdata (_memory_io_dmem_rdata),
+             .io_dmem_wen   (_core_io_dmem_wen),
+             .io_dmem_wdata (_core_io_dmem_wdata),
+             .io_anodes     (io_anodes),
+             .io_segments   (io_segments),
+             .io_exit       (io_exit)
+         );
+    Memory memory (
+               .clock         (clock),
+               .io_imem_addr  (_core_io_imem_addr),
+               .io_imem_inst  (_memory_io_imem_inst),
+               .io_dmem_addr  (_core_io_dmem_addr),
+               .io_dmem_rdata (_memory_io_dmem_rdata),
+               .io_dmem_wen   (_core_io_dmem_wen),
+               .io_dmem_wdata (_core_io_dmem_wdata)
+           );
+endmodule

TopOrigin.sv

@@ -0,0 +1,617 @@
+// Generated by CIRCT firtool-1.62.0
+// VCS coverage exclude_file
+module regfile_32x32(
+  input  [4:0]  R0_addr,
+  input         R0_en,
+                R0_clk,
+  output [31:0] R0_data,
+  input  [4:0]  R1_addr,
+  input         R1_en,
+                R1_clk,
+  output [31:0] R1_data,
+  input  [4:0]  W0_addr,
+  input         W0_en,
+                W0_clk,
+  input  [31:0] W0_data
+);
+
+  reg [31:0] Memory[0:31];
+  always @(posedge W0_clk) begin
+    if (W0_en & 1'h1)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  assign R0_data = R0_en ? Memory[R0_addr] : 32'bx;
+  assign R1_data = R1_en ? Memory[R1_addr] : 32'bx;
+endmodule
+
+module Core(
+  input         clock,
+                reset,
+  output [31:0] io_imem_addr,
+  input  [31:0] io_imem_inst,
+  output [31:0] io_dmem_addr,
+  input  [31:0] io_dmem_rdata,
+  output        io_dmem_wen,
+  output [31:0] io_dmem_wdata,
+  output        io_exit
+);
+
+  wire        exe_jmp_flg;
+  wire        exe_br_flg;
+  wire [31:0] _regfile_ext_R0_data;
+  wire [31:0] _regfile_ext_R1_data;
+  reg  [31:0] id_reg_pc;
+  reg  [31:0] id_reg_inst;
+  reg  [31:0] exe_reg_pc;
+  reg  [4:0]  exe_reg_wb_addr;
+  reg  [31:0] exe_reg_op1_data;
+  reg  [31:0] exe_reg_op2_data;
+  reg  [31:0] exe_reg_rt_data;
+  reg  [4:0]  exe_reg_exe_fun;
+  reg  [1:0]  exe_reg_mem_wen;
+  reg  [1:0]  exe_reg_rf_wen;
+  reg  [2:0]  exe_reg_wb_sel;
+  reg  [31:0] exe_reg_imm_i_sext;
+  reg  [31:0] mem_reg_pc;
+  reg  [4:0]  mem_reg_wb_addr;
+  reg  [31:0] mem_reg_rt_data;
+  reg  [1:0]  mem_reg_mem_wen;
+  reg  [1:0]  mem_reg_rf_wen;
+  reg  [2:0]  mem_reg_wb_sel;
+  reg  [31:0] mem_reg_alu_out;
+  reg  [4:0]  wb_reg_wb_addr;
+  reg  [1:0]  wb_reg_rf_wen;
+  reg  [31:0] wb_reg_wb_data;
+  reg  [31:0] if_reg_pc;
+  wire        _id_inst_T = exe_br_flg | exe_jmp_flg;
+  wire        _id_rt_data_T_2 = exe_reg_rf_wen == 2'h1;
+  wire        stall_flg =
+    _id_rt_data_T_2 & (|(id_reg_inst[25:21])) & id_reg_inst[25:21] == exe_reg_wb_addr
+    | _id_rt_data_T_2 & (|(id_reg_inst[20:16])) & id_reg_inst[20:16] == exe_reg_wb_addr;
+  wire [31:0] id_inst = _id_inst_T | stall_flg ? 32'h20000000 : id_reg_inst;
+  wire        _id_rt_data_T_8 = wb_reg_rf_wen == 2'h1;
+  wire        _exe_alu_out_T = exe_reg_exe_fun == 5'h1;
+  wire [31:0] _exe_alu_out_T_1 = exe_reg_op1_data + exe_reg_op2_data;
+  wire        _exe_alu_out_T_3 = exe_reg_exe_fun == 5'h2;
+  wire [31:0] _exe_alu_out_T_4 = exe_reg_op1_data - exe_reg_op2_data;
+  wire        _exe_alu_out_T_6 = exe_reg_exe_fun == 5'h3;
+  wire [31:0] _exe_alu_out_T_7 = exe_reg_op1_data & exe_reg_op2_data;
+  wire        _exe_alu_out_T_8 = exe_reg_exe_fun == 5'h4;
+  wire [31:0] _exe_alu_out_T_9 = exe_reg_op1_data | exe_reg_op2_data;
+  wire        _exe_alu_out_T_10 = exe_reg_exe_fun == 5'h5;
+  wire [31:0] _exe_alu_out_T_11 = exe_reg_op1_data ^ exe_reg_op2_data;
+  wire        _exe_alu_out_T_12 = exe_reg_exe_fun == 5'h6;
+  wire [62:0] _exe_alu_out_T_14 = {31'h0, exe_reg_op1_data} << exe_reg_op2_data[4:0];
+  wire        _exe_alu_out_T_16 = exe_reg_exe_fun == 5'h7;
+  wire [31:0] _GEN = {27'h0, exe_reg_op2_data[4:0]};
+  wire [31:0] _exe_alu_out_T_18 = exe_reg_op1_data >> _GEN;
+  wire        _exe_alu_out_T_19 = exe_reg_exe_fun == 5'h8;
+  wire [31:0] _exe_alu_out_T_22 = $signed($signed(exe_reg_op1_data) >>> _GEN);
+  wire        _exe_alu_out_T_24 = exe_reg_exe_fun == 5'h9;
+  wire        _exe_alu_out_T_28 = exe_reg_exe_fun == 5'hD;
+  wire [31:0] _exe_alu_out_T_29 = _exe_alu_out_T_28 ? exe_reg_op1_data : 32'h0;
+  wire [31:0] _GEN_0 = {31'h0, $signed(exe_reg_op1_data) < $signed(exe_reg_op2_data)};
+  wire [31:0] exe_alu_out =
+    _exe_alu_out_T
+      ? _exe_alu_out_T_1
+      : _exe_alu_out_T_3
+          ? _exe_alu_out_T_4
+          : _exe_alu_out_T_6
+              ? _exe_alu_out_T_7
+              : _exe_alu_out_T_8
+                  ? _exe_alu_out_T_9
+                  : _exe_alu_out_T_10
+                      ? _exe_alu_out_T_11
+                      : _exe_alu_out_T_12
+                          ? _exe_alu_out_T_14[31:0]
+                          : _exe_alu_out_T_16
+                              ? _exe_alu_out_T_18
+                              : _exe_alu_out_T_19
+                                  ? _exe_alu_out_T_22
+                                  : _exe_alu_out_T_24 ? _GEN_0 : _exe_alu_out_T_29;
+  assign exe_br_flg =
+    exe_reg_exe_fun == 5'hB
+      ? exe_reg_op1_data == exe_reg_op2_data
+      : exe_reg_exe_fun == 5'hC & exe_reg_op1_data != exe_reg_op2_data;
+  assign exe_jmp_flg = exe_reg_wb_sel == 3'h3;
+  wire [31:0] mem_wb_data =
+    mem_reg_wb_sel == 3'h2
+      ? io_dmem_rdata
+      : mem_reg_wb_sel == 3'h3 ? mem_reg_pc + 32'h4 : mem_reg_alu_out;
+  always @(posedge clock) begin
+    if (reset) begin
+      id_reg_pc <= 32'h0;
+      id_reg_inst <= 32'h0;
+      exe_reg_pc <= 32'h0;
+      exe_reg_wb_addr <= 5'h0;
+      exe_reg_op1_data <= 32'h0;
+      exe_reg_op2_data <= 32'h0;
+      exe_reg_rt_data <= 32'h0;
+      exe_reg_exe_fun <= 5'h0;
+      exe_reg_mem_wen <= 2'h0;
+      exe_reg_rf_wen <= 2'h0;
+      exe_reg_wb_sel <= 3'h0;
+      exe_reg_imm_i_sext <= 32'h0;
+      mem_reg_pc <= 32'h0;
+      mem_reg_wb_addr <= 5'h0;
+      mem_reg_rt_data <= 32'h0;
+      mem_reg_mem_wen <= 2'h0;
+      mem_reg_rf_wen <= 2'h0;
+      mem_reg_wb_sel <= 3'h0;
+      mem_reg_alu_out <= 32'h0;
+      wb_reg_wb_addr <= 5'h0;
+      wb_reg_rf_wen <= 2'h0;
+      wb_reg_wb_data <= 32'h0;
+      if_reg_pc <= 32'h0;
+    end
+    else begin
+      automatic logic        _id_rt_data_T_5;
+      automatic logic        _id_rt_data_T;
+      automatic logic        _id_rt_data_T_3;
+      automatic logic        _id_rt_data_T_6;
+      automatic logic        _id_rt_data_T_9;
+      automatic logic [31:0] id_imm_i_sext;
+      automatic logic        _csignals_T_1 = id_inst[31:26] == 6'h23;
+      automatic logic        _csignals_T_3;
+      automatic logic [11:0] _GEN_1 = {id_inst[31:26], id_inst[5:0]};
+      automatic logic        _csignals_T_5 = _GEN_1 == 12'h20;
+      automatic logic        _csignals_T_7 = id_inst[31:26] == 6'h8;
+      automatic logic        _csignals_T_9;
+      automatic logic        _csignals_T_11;
+      automatic logic        _csignals_T_13;
+      automatic logic        _csignals_T_15;
+      automatic logic        _csignals_T_17;
+      automatic logic        _csignals_T_19;
+      automatic logic        _csignals_T_21;
+      automatic logic        _csignals_T_23;
+      automatic logic        _csignals_T_25;
+      automatic logic [16:0] _GEN_2 = {id_inst[31:21], id_inst[5:0]};
+      automatic logic        _csignals_T_27;
+      automatic logic        _csignals_T_29;
+      automatic logic        _csignals_T_31;
+      automatic logic        _csignals_T_33;
+      automatic logic        _csignals_T_35;
+      automatic logic        _GEN_3;
+      automatic logic        _GEN_4;
+      automatic logic [1:0]  csignals_1;
+      automatic logic [2:0]  csignals_2;
+      automatic logic        _GEN_5;
+      automatic logic        _GEN_6;
+      _id_rt_data_T_5 = mem_reg_rf_wen == 2'h1;
+      _id_rt_data_T = id_inst[20:16] == 5'h0;
+      _id_rt_data_T_3 = id_inst[20:16] == exe_reg_wb_addr & _id_rt_data_T_2;
+      _id_rt_data_T_6 = id_inst[20:16] == mem_reg_wb_addr & _id_rt_data_T_5;
+      _id_rt_data_T_9 = id_inst[20:16] == wb_reg_wb_addr & _id_rt_data_T_8;
+      id_imm_i_sext = {{16{id_inst[15]}}, id_inst[15:0]};
+      _csignals_T_3 = id_inst[31:26] == 6'h2B;
+      _csignals_T_9 = _GEN_1 == 12'h22;
+      _csignals_T_11 = _GEN_1 == 12'h24;
+      _csignals_T_13 = _GEN_1 == 12'h25;
+      _csignals_T_15 = _GEN_1 == 12'h26;
+      _csignals_T_17 = id_inst[31:26] == 6'hC;
+      _csignals_T_19 = id_inst[31:26] == 6'hD;
+      _csignals_T_21 = _GEN_1 == 12'h2A;
+      _csignals_T_23 = id_inst[31:26] == 6'h4;
+      _csignals_T_25 = id_inst[31:26] == 6'h5;
+      _csignals_T_27 = _GEN_2 == 17'h0;
+      _csignals_T_29 = _GEN_2 == 17'h2;
+      _csignals_T_31 = _GEN_2 == 17'h3;
+      _csignals_T_33 = id_inst[31:26] == 6'h3;
+      _csignals_T_35 = _GEN_1 == 12'h8;
+      _GEN_3 = _csignals_T_27 | _csignals_T_29 | _csignals_T_31;
+      _GEN_4 = _csignals_T_21 | _csignals_T_23 | _csignals_T_25 | _GEN_3;
+      csignals_1 =
+        _csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7 | _csignals_T_9
+        | _csignals_T_11 | _csignals_T_13 | _csignals_T_15 | _csignals_T_17
+        | _csignals_T_19 | _GEN_4 | ~_csignals_T_33
+          ? 2'h1
+          : 2'h2;
+      csignals_2 =
+        _csignals_T_1 | _csignals_T_3
+          ? 3'h2
+          : _csignals_T_5
+              ? 3'h1
+              : _csignals_T_7
+                  ? 3'h2
+                  : _csignals_T_9 | _csignals_T_11 | _csignals_T_13 | _csignals_T_15
+                      ? 3'h1
+                      : _csignals_T_17 | _csignals_T_19
+                          ? 3'h2
+                          : _GEN_4
+                              ? 3'h1
+                              : _csignals_T_33 ? 3'h4 : {2'h0, ~_csignals_T_35};
+      _GEN_5 = _csignals_T_23 | _csignals_T_25;
+      _GEN_6 =
+        _csignals_T_5 | _csignals_T_7 | _csignals_T_9 | _csignals_T_11 | _csignals_T_13
+        | _csignals_T_15 | _csignals_T_17 | _csignals_T_19 | _csignals_T_21;
+      if (~stall_flg)
+        id_reg_pc <= if_reg_pc;
+      if (_id_inst_T)
+        id_reg_inst <= 32'h20000000;
+      else if (~stall_flg)
+        id_reg_inst <= io_imem_inst;
+      exe_reg_pc <= id_reg_pc;
+      if ((_csignals_T_1
+             ? 3'h2
+             : _csignals_T_3
+                 ? 3'h0
+                 : _GEN_6
+                     ? 3'h1
+                     : _GEN_5
+                         ? 3'h0
+                         : _GEN_3 ? 3'h1 : _csignals_T_33 ? 3'h3 : 3'h0) == 3'h1
+          & id_inst[31:26] == 6'h0)
+        exe_reg_wb_addr <= id_inst[15:11];
+      else if (id_inst[31:26] == 6'h3)
+        exe_reg_wb_addr <= 5'h1F;
+      else
+        exe_reg_wb_addr <= id_inst[20:16];
+      if (csignals_1 == 2'h1) begin
+        if (id_inst[25:21] == 5'h0)
+          exe_reg_op1_data <= 32'h0;
+        else if (id_inst[25:21] == exe_reg_wb_addr & _id_rt_data_T_2) begin
+          if (_exe_alu_out_T)
+            exe_reg_op1_data <= _exe_alu_out_T_1;
+          else if (_exe_alu_out_T_3)
+            exe_reg_op1_data <= _exe_alu_out_T_4;
+          else if (_exe_alu_out_T_6)
+            exe_reg_op1_data <= _exe_alu_out_T_7;
+          else if (_exe_alu_out_T_8)
+            exe_reg_op1_data <= _exe_alu_out_T_9;
+          else if (_exe_alu_out_T_10)
+            exe_reg_op1_data <= _exe_alu_out_T_11;
+          else if (_exe_alu_out_T_12)
+            exe_reg_op1_data <= _exe_alu_out_T_14[31:0];
+          else if (_exe_alu_out_T_16)
+            exe_reg_op1_data <= _exe_alu_out_T_18;
+          else if (_exe_alu_out_T_19)
+            exe_reg_op1_data <= _exe_alu_out_T_22;
+          else if (_exe_alu_out_T_24)
+            exe_reg_op1_data <= _GEN_0;
+          else if (~_exe_alu_out_T_28)
+            exe_reg_op1_data <= 32'h0;
+        end
+        else if (id_inst[25:21] == mem_reg_wb_addr & _id_rt_data_T_5)
+          exe_reg_op1_data <= mem_wb_data;
+        else if (id_inst[25:21] == wb_reg_wb_addr & _id_rt_data_T_8)
+          exe_reg_op1_data <= wb_reg_wb_data;
+        else
+          exe_reg_op1_data <= _regfile_ext_R1_data;
+      end
+      else if (csignals_1 == 2'h2)
+        exe_reg_op1_data <= id_reg_pc;
+      else
+        exe_reg_op1_data <= 32'h0;
+      if (csignals_2 == 3'h1) begin
+        if (_id_rt_data_T)
+          exe_reg_op2_data <= 32'h0;
+        else if (_id_rt_data_T_3) begin
+          if (_exe_alu_out_T)
+            exe_reg_op2_data <= _exe_alu_out_T_1;
+          else if (_exe_alu_out_T_3)
+            exe_reg_op2_data <= _exe_alu_out_T_4;
+          else if (_exe_alu_out_T_6)
+            exe_reg_op2_data <= _exe_alu_out_T_7;
+          else if (_exe_alu_out_T_8)
+            exe_reg_op2_data <= _exe_alu_out_T_9;
+          else if (_exe_alu_out_T_10)
+            exe_reg_op2_data <= _exe_alu_out_T_11;
+          else if (_exe_alu_out_T_12)
+            exe_reg_op2_data <= _exe_alu_out_T_14[31:0];
+          else if (_exe_alu_out_T_16)
+            exe_reg_op2_data <= _exe_alu_out_T_18;
+          else if (_exe_alu_out_T_19)
+            exe_reg_op2_data <= _exe_alu_out_T_22;
+          else if (_exe_alu_out_T_24)
+            exe_reg_op2_data <= _GEN_0;
+          else
+            exe_reg_op2_data <= _exe_alu_out_T_29;
+        end
+        else if (_id_rt_data_T_6)
+          exe_reg_op2_data <= mem_wb_data;
+        else if (_id_rt_data_T_9)
+          exe_reg_op2_data <= wb_reg_wb_data;
+        else
+          exe_reg_op2_data <= _regfile_ext_R0_data;
+      end
+      else if (csignals_2 == 3'h2)
+        exe_reg_op2_data <= id_imm_i_sext;
+      else if (csignals_2 == 3'h4)
+        exe_reg_op2_data <= {4'h0, id_inst[25:0], 2'h0};
+      else
+        exe_reg_op2_data <= 32'h0;
+      exe_reg_rt_data <=
+        _id_rt_data_T
+          ? 32'h0
+          : _id_rt_data_T_3
+              ? exe_alu_out
+              : _id_rt_data_T_6
+                  ? mem_wb_data
+                  : _id_rt_data_T_9 ? wb_reg_wb_data : _regfile_ext_R0_data;
+      if (_csignals_T_1 | _csignals_T_3 | _csignals_T_5 | _csignals_T_7)
+        exe_reg_exe_fun <= 5'h1;
+      else if (_csignals_T_9)
+        exe_reg_exe_fun <= 5'h2;
+      else if (_csignals_T_11)
+        exe_reg_exe_fun <= 5'h3;
+      else if (_csignals_T_13)
+        exe_reg_exe_fun <= 5'h4;
+      else if (_csignals_T_15)
+        exe_reg_exe_fun <= 5'h5;
+      else if (_csignals_T_17)
+        exe_reg_exe_fun <= 5'h3;
+      else if (_csignals_T_19)
+        exe_reg_exe_fun <= 5'h4;
+      else if (_csignals_T_21)
+        exe_reg_exe_fun <= 5'h9;
+      else if (_csignals_T_23)
+        exe_reg_exe_fun <= 5'hB;
+      else if (_csignals_T_25)
+        exe_reg_exe_fun <= 5'hC;
+      else if (_csignals_T_27)
+        exe_reg_exe_fun <= 5'h6;
+      else if (_csignals_T_29)
+        exe_reg_exe_fun <= 5'h7;
+      else if (_csignals_T_31)
+        exe_reg_exe_fun <= 5'h8;
+      else if (_csignals_T_33)
+        exe_reg_exe_fun <= 5'h1;
+      else if (_csignals_T_35)
+        exe_reg_exe_fun <= 5'hD;
+      else
+        exe_reg_exe_fun <= 5'h0;
+      exe_reg_mem_wen <= _csignals_T_1 ? 2'h0 : {1'h0, _csignals_T_3};
+      if (_csignals_T_1) begin
+        exe_reg_rf_wen <= 2'h1;
+        exe_reg_wb_sel <= 3'h2;
+      end
+      else if (_csignals_T_3) begin
+        exe_reg_rf_wen <= 2'h0;
+        exe_reg_wb_sel <= 3'h0;
+      end
+      else if (_GEN_6) begin
+        exe_reg_rf_wen <= 2'h1;
+        exe_reg_wb_sel <= 3'h1;
+      end
+      else if (_GEN_5) begin
+        exe_reg_rf_wen <= 2'h0;
+        exe_reg_wb_sel <= 3'h0;
+      end
+      else begin
+        exe_reg_rf_wen <=
+          {1'h0, _csignals_T_27 | _csignals_T_29 | _csignals_T_31 | _csignals_T_33};
+        if (_GEN_3)
+          exe_reg_wb_sel <= 3'h1;
+        else if (_csignals_T_33)
+          exe_reg_wb_sel <= 3'h3;
+        else
+          exe_reg_wb_sel <= 3'h0;
+      end
+      exe_reg_imm_i_sext <= id_imm_i_sext;
+      mem_reg_pc <= exe_reg_pc;
+      mem_reg_wb_addr <= exe_reg_wb_addr;
+      mem_reg_rt_data <= exe_reg_rt_data;
+      mem_reg_mem_wen <= exe_reg_mem_wen;
+      mem_reg_rf_wen <= exe_reg_rf_wen;
+      mem_reg_wb_sel <= exe_reg_wb_sel;
+      mem_reg_alu_out <= exe_alu_out;
+      wb_reg_wb_addr <= mem_reg_wb_addr;
+      wb_reg_rf_wen <= mem_reg_rf_wen;
+      wb_reg_wb_data <= mem_wb_data;
+      if (exe_br_flg)
+        if_reg_pc <= {exe_reg_imm_i_sext[29:0], 2'h0} + exe_reg_pc;
+      else if (exe_jmp_flg)
+        if_reg_pc <= exe_alu_out;
+      else if (~stall_flg)
+        if_reg_pc <= if_reg_pc + 32'h4;
+    end
+  end // always @(posedge)
+  regfile_32x32 regfile_ext (
+    .R0_addr (id_inst[20:16]),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_regfile_ext_R0_data),
+    .R1_addr (id_inst[25:21]),
+    .R1_en   (1'h1),
+    .R1_clk  (clock),
+    .R1_data (_regfile_ext_R1_data),
+    .W0_addr (wb_reg_wb_addr),
+    .W0_en   (_id_rt_data_T_8 & (|wb_reg_wb_addr)),
+    .W0_clk  (clock),
+    .W0_data (wb_reg_wb_data)
+  );
+  assign io_imem_addr = if_reg_pc;
+  assign io_dmem_addr = mem_reg_alu_out;
+  assign io_dmem_wen = mem_reg_mem_wen[0];
+  assign io_dmem_wdata = mem_reg_rt_data;
+  assign io_exit = id_reg_inst == 32'h114514;
+endmodule
+
+// VCS coverage exclude_file
+module mem_4096x8(
+  input  [11:0] R0_addr,
+  input         R0_en,
+                R0_clk,
+  output [7:0]  R0_data,
+  input  [11:0] R1_addr,
+  input         R1_en,
+                R1_clk,
+  output [7:0]  R1_data,
+  input  [11:0] R2_addr,
+  input         R2_en,
+                R2_clk,
+  output [7:0]  R2_data,
+  input  [11:0] R3_addr,
+  input         R3_en,
+                R3_clk,
+  output [7:0]  R3_data,
+  input  [11:0] R4_addr,
+  input         R4_en,
+                R4_clk,
+  output [7:0]  R4_data,
+  input  [11:0] R5_addr,
+  input         R5_en,
+                R5_clk,
+  output [7:0]  R5_data,
+  input  [11:0] R6_addr,
+  input         R6_en,
+                R6_clk,
+  output [7:0]  R6_data,
+  input  [11:0] R7_addr,
+  input         R7_en,
+                R7_clk,
+  output [7:0]  R7_data,
+  input  [11:0] W0_addr,
+  input         W0_en,
+                W0_clk,
+  input  [7:0]  W0_data,
+  input  [11:0] W1_addr,
+  input         W1_en,
+                W1_clk,
+  input  [7:0]  W1_data,
+  input  [11:0] W2_addr,
+  input         W2_en,
+                W2_clk,
+  input  [7:0]  W2_data,
+  input  [11:0] W3_addr,
+  input         W3_en,
+                W3_clk,
+  input  [7:0]  W3_data
+);
+
+  reg [7:0] Memory[0:4095];
+  always @(posedge W0_clk) begin
+    if (W0_en & 1'h1)
+      Memory[W0_addr] <= W0_data;
+    if (W1_en & 1'h1)
+      Memory[W1_addr] <= W1_data;
+    if (W2_en & 1'h1)
+      Memory[W2_addr] <= W2_data;
+    if (W3_en & 1'h1)
+      Memory[W3_addr] <= W3_data;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_MEM_
+    initial
+      $readmemh("src/hex/mem.hex", Memory);
+  `endif // ENABLE_INITIAL_MEM_
+  assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;
+  assign R1_data = R1_en ? Memory[R1_addr] : 8'bx;
+  assign R2_data = R2_en ? Memory[R2_addr] : 8'bx;
+  assign R3_data = R3_en ? Memory[R3_addr] : 8'bx;
+  assign R4_data = R4_en ? Memory[R4_addr] : 8'bx;
+  assign R5_data = R5_en ? Memory[R5_addr] : 8'bx;
+  assign R6_data = R6_en ? Memory[R6_addr] : 8'bx;
+  assign R7_data = R7_en ? Memory[R7_addr] : 8'bx;
+endmodule
+
+module Memory(
+  input         clock,
+  input  [31:0] io_imem_addr,
+  output [31:0] io_imem_inst,
+  input  [31:0] io_dmem_addr,
+  output [31:0] io_dmem_rdata,
+  input         io_dmem_wen,
+  input  [31:0] io_dmem_wdata
+);
+
+  wire [7:0]  _mem_ext_R0_data;
+  wire [7:0]  _mem_ext_R1_data;
+  wire [7:0]  _mem_ext_R2_data;
+  wire [7:0]  _mem_ext_R3_data;
+  wire [7:0]  _mem_ext_R4_data;
+  wire [7:0]  _mem_ext_R5_data;
+  wire [7:0]  _mem_ext_R6_data;
+  wire [7:0]  _mem_ext_R7_data;
+  wire [11:0] _io_dmem_rdata_T = io_dmem_addr[11:0] + 12'h3;
+  wire [11:0] _io_dmem_rdata_T_3 = io_dmem_addr[11:0] + 12'h2;
+  wire [11:0] _io_dmem_rdata_T_6 = io_dmem_addr[11:0] + 12'h1;
+  mem_4096x8 mem_ext (
+    .R0_addr (io_imem_addr[11:0]),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_mem_ext_R0_data),
+    .R1_addr (io_imem_addr[11:0] + 12'h1),
+    .R1_en   (1'h1),
+    .R1_clk  (clock),
+    .R1_data (_mem_ext_R1_data),
+    .R2_addr (io_imem_addr[11:0] + 12'h2),
+    .R2_en   (1'h1),
+    .R2_clk  (clock),
+    .R2_data (_mem_ext_R2_data),
+    .R3_addr (io_imem_addr[11:0] + 12'h3),
+    .R3_en   (1'h1),
+    .R3_clk  (clock),
+    .R3_data (_mem_ext_R3_data),
+    .R4_addr (io_dmem_addr[11:0]),
+    .R4_en   (1'h1),
+    .R4_clk  (clock),
+    .R4_data (_mem_ext_R4_data),
+    .R5_addr (_io_dmem_rdata_T_6),
+    .R5_en   (1'h1),
+    .R5_clk  (clock),
+    .R5_data (_mem_ext_R5_data),
+    .R6_addr (_io_dmem_rdata_T_3),
+    .R6_en   (1'h1),
+    .R6_clk  (clock),
+    .R6_data (_mem_ext_R6_data),
+    .R7_addr (_io_dmem_rdata_T),
+    .R7_en   (1'h1),
+    .R7_clk  (clock),
+    .R7_data (_mem_ext_R7_data),
+    .W0_addr (_io_dmem_rdata_T),
+    .W0_en   (io_dmem_wen),
+    .W0_clk  (clock),
+    .W0_data (io_dmem_wdata[31:24]),
+    .W1_addr (_io_dmem_rdata_T_3),
+    .W1_en   (io_dmem_wen),
+    .W1_clk  (clock),
+    .W1_data (io_dmem_wdata[23:16]),
+    .W2_addr (_io_dmem_rdata_T_6),
+    .W2_en   (io_dmem_wen),
+    .W2_clk  (clock),
+    .W2_data (io_dmem_wdata[15:8]),
+    .W3_addr (io_dmem_addr[11:0]),
+    .W3_en   (io_dmem_wen),
+    .W3_clk  (clock),
+    .W3_data (io_dmem_wdata[7:0])
+  );
+  assign io_imem_inst =
+    {_mem_ext_R3_data, _mem_ext_R2_data, _mem_ext_R1_data, _mem_ext_R0_data};
+  assign io_dmem_rdata =
+    {_mem_ext_R7_data, _mem_ext_R6_data, _mem_ext_R5_data, _mem_ext_R4_data};
+endmodule
+
+module TopOrigin(
+  input  clock,
+         reset,
+  output io_exit
+);
+
+  wire [31:0] _memory_io_imem_inst;
+  wire [31:0] _memory_io_dmem_rdata;
+  wire [31:0] _core_io_imem_addr;
+  wire [31:0] _core_io_dmem_addr;
+  wire        _core_io_dmem_wen;
+  wire [31:0] _core_io_dmem_wdata;
+  Core core (
+    .clock         (clock),
+    .reset         (reset),
+    .io_imem_addr  (_core_io_imem_addr),
+    .io_imem_inst  (_memory_io_imem_inst),
+    .io_dmem_addr  (_core_io_dmem_addr),
+    .io_dmem_rdata (_memory_io_dmem_rdata),
+    .io_dmem_wen   (_core_io_dmem_wen),
+    .io_dmem_wdata (_core_io_dmem_wdata),
+    .io_exit       (io_exit)
+  );
+  Memory memory (
+    .clock         (clock),
+    .io_imem_addr  (_core_io_imem_addr),
+    .io_imem_inst  (_memory_io_imem_inst),
+    .io_dmem_addr  (_core_io_dmem_addr),
+    .io_dmem_rdata (_memory_io_dmem_rdata),
+    .io_dmem_wen   (_core_io_dmem_wen),
+    .io_dmem_wdata (_core_io_dmem_wdata)
+  );
+endmodule
+

build.sbt

@@ -1,8 +1,8 @@
 // See README.md for license details.
 
-ThisBuild / scalaVersion     := "2.13.12"
-ThisBuild / version          := "0.1.0"
-ThisBuild / organization     := "%ORGANIZATION%"
+ThisBuild / scalaVersion := "2.13.12"
+ThisBuild / version := "0.1.0"
+ThisBuild / organization := "%ORGANIZATION%"
 
 val chiselVersion = "6.2.0"
 
@@ -11,14 +11,17 @@ lazy val root = (project in file("."))
     name := "%NAME%",
     libraryDependencies ++= Seq(
       "org.chipsalliance" %% "chisel" % chiselVersion,
-      "org.scalatest" %% "scalatest" % "3.2.16" % "test",
+      "edu.berkeley.cs" %% "chiseltest" % "6.0.0" % "test",
+      "org.scalatest" %% "scalatest" % "3.2.16" % "test"
     ),
     scalacOptions ++= Seq(
       "-language:reflectiveCalls",
       "-deprecation",
       "-feature",
       "-Xcheckinit",
-      "-Ymacro-annotations",
+      "-Ymacro-annotations"
     ),
-    addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full),
+    addCompilerPlugin(
+      "org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full
+    )
   )

micore.xdc

@@ -0,0 +1,30 @@
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+set_property PACKAGE_PIN W5 [get_ports clock] 
+set_property IOSTANDARD LVCMOS33 [get_ports clock] 
+set_property PACKAGE_PIN V17 [get_ports reset] 
+set_property IOSTANDARD LVCMOS33 [get_ports reset] 
+set_property PACKAGE_PIN E19 [get_ports io_exit]
+set_property IOSTANDARD LVCMOS33 [get_ports io_exit]
+set_property PACKAGE_PIN U2 [get_ports {io_anodes[0]}]
+set_property PACKAGE_PIN U4 [get_ports {io_anodes[1]}]
+set_property PACKAGE_PIN V4 [get_ports {io_anodes[2]}]
+set_property PACKAGE_PIN W4 [get_ports {io_anodes[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_anodes[3]}]
+
+set_property PACKAGE_PIN U7 [get_ports {io_segments[0]}]
+set_property PACKAGE_PIN V5 [get_ports {io_segments[1]}]
+set_property PACKAGE_PIN U5 [get_ports {io_segments[2]}]
+set_property PACKAGE_PIN V8 [get_ports {io_segments[3]}]
+set_property PACKAGE_PIN U8 [get_ports {io_segments[4]}]
+set_property PACKAGE_PIN W6 [get_ports {io_segments[5]}]
+set_property PACKAGE_PIN W7 [get_ports {io_segments[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {io_segments[6]}]

project/project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp

@@ -1 +1 @@
-{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
+{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}

project/project/project/target/streams/_global/update/_global/streams/out

@@ -1,3 +1,3 @@
 [debug] not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/project/"), "micore-build-build-build")...
-[debug] Done updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/project/"), "micore-build-build-build")
+[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")...
+[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/"), "micore-build-build-build")

project/project/project/target/streams/compile/_global/_global/compileOutputs/previous

@@ -1 +1 @@
-["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

project/project/project/target/streams/compile/exportedProducts/_global/streams/export

@@ -1 +1 @@
-/home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
+/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

project/project/project/target/streams/compile/incOptions/_global/streams/out

@@ -1,5 +1,5 @@
-[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
 [debug] About to delete class files:
 [debug] We backup class files:
-[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
-[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes.bak

project/project/project/target/streams/runtime/exportedProducts/_global/streams/export

@@ -1 +1 @@
-/home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
+/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

project/project/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export

@@ -1 +1 @@
-/home/gh0s7/project/ddca/micore/project/project/project/target/scala-2.12/sbt-1.0/classes
+/run/media/gh0s7/Data/project/ddca2024/micore/project/project/project/target/scala-2.12/sbt-1.0/classes

project/project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp

@@ -1 +1 @@
-{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/home/gh0s7/project/ddca/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}
+{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.18\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"},"{\"organization\":\"ch.epfl.scala\",\"name\":\"sbt-bloop\",\"revision\":\"2.0.6\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/run/media/gh0s7/Data/project/ddca2024/micore/project/project/metals.sbt","range":{"$fields":["start","end"],"start":6,"end":7}},"type":"RangePosition"}}

project/project/target/streams/_global/update/_global/streams/out

@@ -1,3 +1,3 @@
 [debug] not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build")...
-[debug] Done updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build")
+[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")...
+[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")

project/project/target/streams/_global/updateClassifiers/_global/streams/out

@@ -1,3 +1,3 @@
 [debug] not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build")...
-[debug] Done updating ProjectRef(uri("file:/home/gh0s7/project/ddca/micore/project/project/"), "micore-build-build")
+[debug] Updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")...
+[debug] Done updating ProjectRef(uri("file:/run/media/gh0s7/Data/project/ddca2024/micore/project/project/"), "micore-build-build")

project/project/target/streams/compile/_global/_global/compileOutputs/previous

@@ -1 +1 @@
-["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]
+["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/zinc/inc_compile_2.12.zip"]]

project/project/target/streams/compile/bloopGenerate/_global/streams/out

@@ -1,4 +1,4 @@
 [debug] [micore-build-build] Classpath dependencies List()
 [debug] [micore-build-build] Dependencies from configurations List()
-[debug] Bloop wrote the configuration of project 'micore-build-build' to '/home/gh0s7/project/ddca/micore/project/project/.bloop/micore-build-build.json'
+[debug] Bloop wrote the configuration of project 'micore-build-build' to '/run/media/gh0s7/Data/project/ddca2024/micore/project/project/.bloop/micore-build-build.json'
 [success] Generated .bloop/micore-build-build.json

project/project/target/streams/compile/exportedProducts/_global/streams/export

@@ -1 +1 @@
-/home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/classes
+/run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes

project/project/target/streams/compile/incOptions/_global/streams/out

@@ -1,5 +1,5 @@
-[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
 [debug] About to delete class files:
 [debug] We backup class files:
-[debug] Created transactional ClassFileManager with tempDir = /home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
-[debug] Removing the temporary directory used for backing up class files: /home/gh0s7/project/ddca/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Created transactional ClassFileManager with tempDir = /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak
+[debug] Removing the temporary directory used for backing up class files: /run/media/gh0s7/Data/project/ddca2024/micore/project/project/target/scala-2.12/sbt-1.0/classes.bak