Core.scala Update

.gitignore

@@ -4,7 +4,9 @@
 .history
 .metals
 .bloop
+.scalafmt.conf
 *.code-workspace
+target
 
 # virtual machine crash logs, see http://www.java.com/en/download/help/error_hotspot.xml
 hs_err_pid*

GCD.sv

@@ -1,27 +0,0 @@
-// Generated by CIRCT firtool-1.62.0
-module GCD(
-  input         clock,
-                reset,
-  input  [15:0] io_value1,
-                io_value2,
-  input         io_loadingValues,
-  output [15:0] io_outputGCD,
-  output        io_outputValid
-);
-
-  reg [15:0] x;
-  reg [15:0] y;
-  always @(posedge clock) begin
-    if (io_loadingValues) begin
-      x <= io_value1;
-      y <= io_value2;
-    end
-    else if (x > y)
-      x <= x - y;
-    else
-      y <= y - x;
-  end // always @(posedge)
-  assign io_outputGCD = x;
-  assign io_outputValid = y == 16'h0;
-endmodule
-

src/main/scala/common/Consts.scala

@@ -28,7 +28,7 @@ object Consts {
   val ALU_SLTU = 10.U(EXE_FUN_LEN.W) // 无符号比较小于操作
   val BR_BEQ = 11.U(EXE_FUN_LEN.W) // 分支相等
   val BR_BNE = 12.U(EXE_FUN_LEN.W) // 分支不等
-  val ALU_JALR = 13.U(EXE_FUN_LEN.W) // JALR跳转
+  val ALU_JAL = 13.U(EXE_FUN_LEN.W) // JAL跳转
   val ALU_COPY1 = 14.U(EXE_FUN_LEN.W) // 复制操作
 
   // 操作数选择

src/main/scala/micore/Core.scala

@@ -12,4 +12,86 @@ class Core extends Module {
     val dmem = Flipped(new DmemPortIo)
     val exit = Output(Bool())
   })
+
+  val regfile = Mem(32, UInt(WORD_LEN.W))
+
+  // ********* Pipeline Registers *********
+  // IF/ID state
+  val id_reg_pc = RegInit(0.U(WORD_LEN.W))
+  val id_reg_inst = RegInit(0.U(WORD_LEN.W))
+
+  // ID/EX state
+  val exe_reg_pc = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
+  val exe_reg_op1_data = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_op2_data = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_rs2_data = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_exe_fun = RegInit(0.U(EXE_FUN_LEN.W))
+  val exe_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
+  val exe_reg_rf_wen = RegInit(0.U(REN_LEN.W))
+  val exe_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W))
+  val exe_reg_imm_i_sext = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_imm_s_sext = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_imm_b_sext = RegInit(0.U(WORD_LEN.W))
+  val exe_reg_imm_u_shifted = RegInit(0.U(WORD_LEN.W))
+
+  // EX/MEM state
+  val mem_reg_pc = RegInit(0.U(WORD_LEN.W))
+  val mem_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
+  val mem_reg_op1_data = RegInit(0.U(WORD_LEN.W))
+  val mem_reg_rs2_data = RegInit(0.U(WORD_LEN.W))
+  val mem_reg_mem_wen = RegInit(0.U(MEN_LEN.W))
+  val mem_reg_rf_wen = RegInit(0.U(REN_LEN.W))
+  val mem_reg_wb_sel = RegInit(0.U(WB_SEL_LEN.W))
+  val mem_reg_alu_out = RegInit(0.U(WORD_LEN.W))
+
+  // MEM/WB state
+  val wb_reg_wb_addr = RegInit(0.U(ADDR_LEN.W))
+  val wb_reg_rf_wen = RegInit(0.U(REN_LEN.W))
+  val wb_reg_wb_data = RegInit(0.U(WORD_LEN.W))
+
+  // ********* Instruction Fetch (IF) Stage *********
+  val if_reg_pc = RegInit(START_ADDR)
+  io.imem.addr := if_reg_pc
+  val if_inst = io.imem.inst
+
+  val stall_flg = Wire(Bool()) // 停顿标志
+  val exe_br_flg = Wire(Bool()) // 跳转标志
+  val exe_br_target = Wire(UInt(WORD_LEN.W)) // 跳转目标地址
+  val exe_jmp_flg = Wire(Bool()) // 跳转标志
+  val exe_alu_out = Wire(UInt(WORD_LEN.W)) // ALU输出
+
+  val if_pc_plus4 = if_reg_pc + 4.U(WORD_LEN.W)
+  val if_pc_next =
+    MuxCase(
+      if_pc_plus4,
+      Seq(
+        exe_br_flg -> exe_br_target,
+        exe_jmp_flg -> exe_alu_out,
+        stall_flg -> if_reg_pc
+      )
+    )
+  if_reg_pc := if_pc_next
+
+  // ********* IF/ID Stage *********
+  id_reg_pc := Mux(stall_flg, id_reg_pc, if_reg_pc)
+  id_reg_inst := MuxCase(
+    if_inst,
+    Seq(
+      (exe_br_flg || exe_jmp_flg) -> BUBBLE,
+      stall_flg -> id_reg_inst
+    )
+  )
+
+  // ********* Decode (ID) Stage *********
+  val id_rs1_addr_b = id_reg_inst(25, 21)
+  val id_rs2_addr_b = id_reg_inst(20, 16)
+
+  // 与EX数据冒险
+  val id_rs1_data_hazard =
+    (exe_reg_rf_wen === REN_S) && (id_rs1_addr_b =/= 0.U) && (id_rs1_addr_b === exe_reg_wb_addr)
+  val id_rs2_data_hazard =
+    (exe_reg_rf_wen === REN_S) && (id_rs2_addr_b =/= 0.U) && (id_rs2_addr_b === exe_reg_wb_addr)
+  stall_flg := (id_rs1_data_hazard || id_rs2_data_hazard)
+
 }