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ubsan: fix undefined shifts

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A signed integer cannot be shifted in a way that will flip the
sign bit; make such arguments unsigned to be safe

Change-Id: Iafc060f98f899ae3ffb876ba22fdd6183fbb6e57
This commit is contained in:
Dominique Martinet
2018-12-26 15:06:32 +09:00
parent d9b2924249
commit bc2a444828
3 changed files with 4 additions and 4 deletions
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4
arch/arm64/kernel/include/arm-gic-v2.h
View File

@@ -60,9 +60,9 @@
#ifdef CONFIG_HAS_NMI #ifdef CONFIG_HAS_NMI
#define GICD_INT_NMI_PRI 0x40 #define GICD_INT_NMI_PRI 0x40
#define GICD_INT_DEF_PRI 0xc0 #define GICD_INT_DEF_PRI 0xc0U
#else #else
#define GICD_INT_DEF_PRI 0xa0 #define GICD_INT_DEF_PRI 0xa0U
#endif #endif
#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\ #define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
(GICD_INT_DEF_PRI << 16) |\ (GICD_INT_DEF_PRI << 16) |\

2
arch/arm64/kernel/include/cputype.h
View File

@@ -36,7 +36,7 @@
(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
#define MIDR_IMPLEMENTOR_SHIFT 24 #define MIDR_IMPLEMENTOR_SHIFT 24
#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) #define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT)
#define MIDR_IMPLEMENTOR(midr) \ #define MIDR_IMPLEMENTOR(midr) \
(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)

2
lib/include/bitops-fls.h
View File

@@ -2,7 +2,7 @@
#ifndef INCLUDE_BITOPS_FLS_H #ifndef INCLUDE_BITOPS_FLS_H
#define INCLUDE_BITOPS_FLS_H #define INCLUDE_BITOPS_FLS_H
static inline int fls(int x) static inline int fls(unsigned int x)
{ {
int r = 32; int r = 32;
if (!x) { if (!x) {