From bc2a4448288ca93d7b7a70f4481bad95b758233b Mon Sep 17 00:00:00 2001
From: Dominique Martinet <dominique.martinet@cea.fr>
Date: Wed, 26 Dec 2018 15:06:32 +0900
Subject: [PATCH] ubsan: fix undefined shifts

A signed integer cannot be shifted in a way that will flip the
sign bit; make such arguments unsigned to be safe

Change-Id: Iafc060f98f899ae3ffb876ba22fdd6183fbb6e57
---
 arch/arm64/kernel/include/arm-gic-v2.h | 4 ++--
 arch/arm64/kernel/include/cputype.h    | 2 +-
 lib/include/bitops-fls.h               | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kernel/include/arm-gic-v2.h b/arch/arm64/kernel/include/arm-gic-v2.h
index 0195af34..25070c9c 100644
--- a/arch/arm64/kernel/include/arm-gic-v2.h
+++ b/arch/arm64/kernel/include/arm-gic-v2.h
@@ -60,9 +60,9 @@
 
 #ifdef CONFIG_HAS_NMI
 #define GICD_INT_NMI_PRI		0x40
-#define GICD_INT_DEF_PRI		0xc0
+#define GICD_INT_DEF_PRI		0xc0U
 #else
-#define GICD_INT_DEF_PRI		0xa0
+#define GICD_INT_DEF_PRI		0xa0U
 #endif
 #define GICD_INT_DEF_PRI_X4		((GICD_INT_DEF_PRI << 24) |\
 					(GICD_INT_DEF_PRI << 16) |\
diff --git a/arch/arm64/kernel/include/cputype.h b/arch/arm64/kernel/include/cputype.h
index bb2243bb..27d9c16c 100644
--- a/arch/arm64/kernel/include/cputype.h
+++ b/arch/arm64/kernel/include/cputype.h
@@ -36,7 +36,7 @@
 	(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
 
 #define MIDR_IMPLEMENTOR_SHIFT	24
-#define MIDR_IMPLEMENTOR_MASK	(0xff << MIDR_IMPLEMENTOR_SHIFT)
+#define MIDR_IMPLEMENTOR_MASK	(0xffU << MIDR_IMPLEMENTOR_SHIFT)
 #define MIDR_IMPLEMENTOR(midr)	\
 	(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
 
diff --git a/lib/include/bitops-fls.h b/lib/include/bitops-fls.h
index 88a8c19f..1be81e79 100644
--- a/lib/include/bitops-fls.h
+++ b/lib/include/bitops-fls.h
@@ -2,7 +2,7 @@
 #ifndef INCLUDE_BITOPS_FLS_H
 #define INCLUDE_BITOPS_FLS_H
 
-static inline int fls(int x)
+static inline int fls(unsigned int x)
 {
 	int r = 32;
 	if (!x) {