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Author SHA1 Message Date
gh0s7 83afaf19ce Skip zero EM resident downloads 2026-05-07 13:04:46 +08:00
gh0s7 cb911dec06 Add EM GPU fast paths and defaults 2026-05-07 12:18:56 +08:00
gh0s7 dd0e20d8c7 Fix BSSN-EScalar CUDA boundary and scalar KO 2026-05-06 15:44:35 +08:00
gh0s7 ffa0d801ed Default Python GPU runner to EScalar fast path 2026-05-06 00:12:46 +08:00
gh0s7 ae64a22178 Complete BSSN-EScalar CUDA resident transfers 2026-05-05 23:57:42 +08:00
gh0s7 85fe29cc2e Optimize BSSN-EScalar CUDA path 2026-05-05 10:47:46 +08:00
ianchb 06f62dee36 Switch back to Intel toolchain as the default option 
Seems that Intel MPI also supports CUDA-aware by setting I_MPI_OFFLOAD to 1. Besides, I_MPI_OFFLOAD_IPC=0 is needed to avoid segfaults.
 2026-05-01 21:59:13 +08:00
gh0s7 35b6ceff02 Broaden cached CUDA sync paths 2026-05-01 18:03:04 +08:00
gh0s7 51f3819892 Save generated source formatting state 2026-04-30 20:47:44 +08:00
gh0s7 a9a3809148 Default Python launcher to fast GPU path 2026-04-30 20:15:34 +08:00
gh0s7 b1974ef146 Stabilize device AMR restrict across regrid 2026-04-30 20:01:18 +08:00
gh0s7 be9033f449 Add optional CUDA surface interpolation 2026-04-30 19:21:19 +08:00
gh0s7 6835608f92 Add configurable analysis MAP cadence 2026-04-30 19:10:12 +08:00
gh0s7 e0d0673c8e Enable optimized GPU runs from Python launcher 2026-04-30 18:31:31 +08:00
gh0s7 da4d56ccf7 Optimize BSSN surface interpolation fast path 2026-04-30 18:25:21 +08:00
gh0s7 a6483d013d Add CUDA AMR restrict diagnostics 2026-04-30 12:20:44 +08:00
gh0s7 8486532920 Add resident BSSN GPU point interpolation 2026-04-30 11:39:15 +08:00
gh0s7 18e9c9cc50 Optimize BSSN CUDA resident AMR prolong path 2026-04-30 10:58:15 +08:00
gh0s7 1ee229a91f Add keyed BSSN CUDA resident banks 2026-04-29 19:44:19 +08:00
gh0s7 68eab03bac Add opt-in BSSN CUDA resident AMR path 2026-04-29 19:15:37 +08:00
gh0s7 090d8657ae Optimize BSSN CUDA state transfers 2026-04-29 18:34:31 +08:00
gh0s7 22c1e7168b Optimize BSSN CUDA resident state and CUDA-aware MPI 2026-04-29 17:05:10 +08:00
ianchb a0dab90bcb Switch to NVIDIA HPC Toolchain 2026-04-29 08:31:49 +08:00
ianchb c689cc8dc9 [WIP] Add CUDA support for Z4C 
Rewritten done by Codex.
This still has errors, do not pick this one now.
 2026-04-27 11:58:43 +08:00
ianchb 60fee8f1c1 Fix Z4C C++ gauge damping ordering 2026-04-26 15:38:13 +08:00
ianchb 843b116954 Add C++ Z4C RHS path and port some BSSN optimizations 2026-04-25 10:39:01 +08:00
ianchb c768e1220b Also disable cached sync for Z4C 2026-04-25 10:25:54 +08:00
gh0s7andianchb 02f149e2e3 Disable cached sync for BSSN-EScalar 2026-04-25 10:17:47 +08:00
gh0s7andianchb 422e8ec4dc Fallback BSSN-EScalar restrict/prolong path 2026-04-25 10:10:34 +08:00
gh0s7andianchb c4909b9843 更新精度检查脚本加入图像比对检查 
(cherry picked from commit ac82ebd889)
 2026-04-25 09:40:12 +08:00
ianchb f521a97563 Fix ABE CPU version build error 2026-04-25 09:39:49 +08:00
ianchb 53c55451b3 Update makefile and scripts for CUDA BSSN configuration and build commands 2026-04-25 09:19:50 +08:00
gh0s7andianchb 768345954f Add optional BSSN kernel profiling switches 
(cherry picked from commit 9c31384b2f)
 2026-04-25 08:39:43 +08:00
gh0s7andianchb 9a6df6438b Remove dead chi derivative setup in BSSN RHS 
(cherry picked from commit e4e741caa1)
 2026-04-25 08:38:01 +08:00
gh0s7andianchb 8e9463aa90 Localize chi Ricci intermediates in RHS 
(cherry picked from commit 65e0f95f40)
 2026-04-25 08:37:41 +08:00
gh0s7andianchb 7c6f15002e Elide dead stores in BSSN RHS hot path 
(cherry picked from commit f9fbf97e64)
 2026-04-25 08:37:40 +08:00
gh0s7andianchb 6410c62e3e Add fine-grained step timing and trim BH RHS overhead 
(cherry picked from commit 968522995b)
 2026-04-25 08:37:19 +08:00
gh0s7andianchb 11977eb82f Merge wave and mass extraction interpolation 
(cherry picked from commit f3988ac8ca)
 2026-04-25 08:25:34 +08:00
gh0s7andianchb cce8a44fc4 Cache wave extraction angular kernels 
(cherry picked from commit e4c25eb21f)
 2026-04-25 08:24:36 +08:00
gh0s7andianchb c589097618 Reuse mass integrand across detector radii 
(cherry picked from commit 4b10519876)
 2026-04-25 08:24:11 +08:00
gh0s7andianchb b713e5a9be Batch constraint norm reductions 
(cherry picked from commit 3a58273501)
 2026-04-25 08:22:00 +08:00
gh0s7andianchb 0396701572 Optimize constraint refresh after regrid 
(cherry picked from commit 5c65cea2f0)
 2026-04-25 08:18:51 +08:00
ianchb bb20c9a876 fix ADM Constrant Violation Analysis 2026-04-15 19:19:16 +08:00
ianchb 8fe60ea703 Add zero matter handling and interpolation for resident state in CUDA BSSN 2026-04-15 00:25:53 +08:00
ianchb 9ab7e7c7f9 Fuse phases 5 and 6 for Gamma_rhs computation and optimize phases 8 and 9 for efficiency 2026-04-14 23:23:04 +08:00
ianchb f9119e8a2a Add resident-GA mode switch and simplify sync logic 2026-04-14 21:09:27 +08:00
ianchb 726d743376 Fuse Ricci assembly and optimize trK/Aij gauge kernels 2026-04-14 19:20:12 +08:00
ianchb af344bf1e5 Add Phase-10 Ricci kernels and batch launch flow 2026-04-14 19:00:22 +08:00
ianchb 7191fc0b96 Move resident sync comm buffers into StepAllocation pool 2026-04-13 21:04:44 +08:00
ianchb b3ec244cf9 Add batched first/second derivative kernels for CUDA RHS 2026-04-13 20:51:08 +08:00