58 lines
2.2 KiB
Verilog
58 lines
2.2 KiB
Verilog
`include "VX_tex_define.vh"
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module VX_tex_format #(
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parameter CORE_ID = 0
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) (
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input wire [`TEX_FORMAT_BITS-1:0] format,
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input wire [31:0] texel_in,
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output wire [31:0] texel_out
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);
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`UNUSED_PARAM (CORE_ID)
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reg [31:0] texel_out_r;
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always @(*) begin
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case (format)
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`TEX_FORMAT_R5G6B5: begin
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texel_out_r[07:00] = `TEX_COLOR_BITS'(texel_in[4:0]);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(texel_in[10:5]);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[15:11]);
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texel_out_r[31:24] = {`TEX_COLOR_BITS{1'b1}};
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end
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`TEX_FORMAT_R4G4B4A4: begin
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texel_out_r[07:00] = `TEX_COLOR_BITS'(texel_in[3:0]);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(texel_in[7:4]);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[11:8]);
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texel_out_r[31:24] = `TEX_COLOR_BITS'(texel_in[15:12]);
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end
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`TEX_FORMAT_L8A8: begin
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texel_out_r[07:00] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[31:24] = `TEX_COLOR_BITS'(texel_in[15:8]);
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end
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`TEX_FORMAT_A8: begin
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texel_out_r[07:00] = `TEX_COLOR_BITS'(0);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(0);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(0);
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texel_out_r[31:24] = `TEX_COLOR_BITS'(texel_in[7:0]);
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end
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`TEX_FORMAT_L8: begin
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texel_out_r[07:00] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[31:24] = {`TEX_COLOR_BITS{1'b1}};
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end
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default: begin // `TEX_FORMAT_R8G8B8A8:
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texel_out_r[07:00] = `TEX_COLOR_BITS'(texel_in[7:0]);
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texel_out_r[15:08] = `TEX_COLOR_BITS'(texel_in[15:8]);
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texel_out_r[23:16] = `TEX_COLOR_BITS'(texel_in[23:16]);
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texel_out_r[31:24] = `TEX_COLOR_BITS'(texel_in[31:24]);
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end
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endcase
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end
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assign texel_out = texel_out_r;
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endmodule
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