86 lines
3.7 KiB
Verilog
86 lines
3.7 KiB
Verilog
`include "VX_platform.vh"
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/// Modified port of lzc module from fpnew Libray
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/// reference: https://github.com/pulp-platform/fpnew
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/// A trailing zero counter / leading zero counter.
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/// Set MODE to 0 for trailing zero counter => cnt_o is the number of trailing zeros (from the LSB)
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/// Set MODE to 1 for leading zero counter => cnt_o is the number of leading zeros (from the MSB)
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/// If the input does not contain a zero, `empty_o` is asserted. Additionally `cnt_o` contains
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/// the maximum number of zeros - 1. For example:
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/// in_i = 000_0000, empty_o = 1, cnt_o = 6 (mode = 0)
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/// in_i = 000_0001, empty_o = 0, cnt_o = 0 (mode = 0)
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/// in_i = 000_1000, empty_o = 0, cnt_o = 3 (mode = 0)
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/// Furthermore, this unit contains a more efficient implementation for Verilator (simulation only).
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/// This speeds up simulation significantly.
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module VX_lzc #(
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/// The width of the input vector.
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parameter int unsigned WIDTH = 2,
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parameter bit MODE = 1'b0 // 0 -> trailing zero, 1 -> leading zero
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) (
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input logic [WIDTH-1:0] in_i,
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output logic [$clog2(WIDTH)-1:0] cnt_o,
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output logic valid_o
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);
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`IGNORE_WARNINGS_BEGIN
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localparam int unsigned NUM_LEVELS = $clog2(WIDTH);
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// pragma translate_off
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initial begin
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assert(WIDTH > 0) else $fatal("input must be at least one bit wide");
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end
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// pragma translate_on
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logic [WIDTH-1:0][NUM_LEVELS-1:0] index_lut;
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logic [2**NUM_LEVELS-1:0] sel_nodes;
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logic [2**NUM_LEVELS-1:0][NUM_LEVELS-1:0] index_nodes;
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logic [WIDTH-1:0] in_tmp;
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// reverse vector if required
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always_comb begin : flip_vector
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for (int unsigned i = 0; i < WIDTH; i++) begin
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in_tmp[i] = (MODE) ? in_i[WIDTH-1-i] : in_i[i];
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end
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end
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for (genvar j = 0; unsigned'(j) < WIDTH; j++) begin : g_index_lut
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assign index_lut[j] = NUM_LEVELS'(unsigned'(j));
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end
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for (genvar level = 0; unsigned'(level) < NUM_LEVELS; level++) begin : g_levels
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if (unsigned'(level) == NUM_LEVELS-1) begin : g_last_level
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for (genvar k = 0; k < 2**level; k++) begin : g_level
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// if two successive indices are still in the vector...
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if (unsigned'(k) * 2 < WIDTH-1) begin
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assign sel_nodes[2**level-1+k] = in_tmp[k*2] | in_tmp[k*2+1];
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assign index_nodes[2**level-1+k] = (in_tmp[k*2] == 1'b1) ? index_lut[k*2] :
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index_lut[k*2+1];
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end
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// if only the first index is still in the vector...
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if (unsigned'(k) * 2 == WIDTH-1) begin
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assign sel_nodes[2**level-1+k] = in_tmp[k*2];
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assign index_nodes[2**level-1+k] = index_lut[k*2];
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end
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// if index is out of range
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if (unsigned'(k) * 2 > WIDTH-1) begin
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assign sel_nodes[2**level-1+k] = 1'b0;
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assign index_nodes[2**level-1+k] = '0;
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end
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end
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end else begin
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for (genvar l = 0; l < 2**level; l++) begin : g_level
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assign sel_nodes[2**level-1+l] = sel_nodes[2**(level+1)-1+l*2] | sel_nodes[2**(level+1)-1+l*2+1];
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assign index_nodes[2**level-1+l] = (sel_nodes[2**(level+1)-1+l*2] == 1'b1) ? index_nodes[2**(level+1)-1+l*2] :
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index_nodes[2**(level+1)-1+l*2+1];
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end
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end
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end
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assign cnt_o = NUM_LEVELS > unsigned'(0) ? index_nodes[0] : $clog2(WIDTH)'(0);
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assign valid_o = NUM_LEVELS > unsigned'(0) ? sel_nodes[0] : (|in_i);
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`IGNORE_WARNINGS_END
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endmodule |