41 lines
1.0 KiB
Verilog
41 lines
1.0 KiB
Verilog
`include "VX_platform.vh"
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module VX_fixed_arbiter #(
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parameter NUM_REQS = 1,
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parameter LOCK_ENABLE = 0,
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parameter LOG_NUM_REQS = $clog2(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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input wire [NUM_REQS-1:0] requests,
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input wire enable,
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output wire [LOG_NUM_REQS-1:0] grant_index,
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output wire [NUM_REQS-1:0] grant_onehot,
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output wire grant_valid
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);
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`UNUSED_PARAM (LOCK_ENABLE)
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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`UNUSED_VAR (enable)
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if (NUM_REQS == 1) begin
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assign grant_index = 0;
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assign grant_onehot = requests;
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assign grant_valid = requests[0];
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end else begin
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VX_priority_encoder #(
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.N (NUM_REQS)
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) tid_select (
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.data_in (requests),
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.index (grant_index),
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.onehot (grant_onehot),
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.valid_out (grant_valid)
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);
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end
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endmodule |