169 lines
3.2 KiB
Verilog
169 lines
3.2 KiB
Verilog
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`define NT 4
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`define NT_M1 (`NT-1)
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// NW_M1 is actually log2(NW)
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`define NW_M1 (3-1)
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`define NW 8
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// Uncomment the below line if NW=1
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// `define ONLY
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// `define SYN 1
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`define ASIC 1
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`define DCACHE_NUM_BANKS 8
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`define DCACHE_NUMBER_BANKS 8
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`define DCACHE_NUM_WORDS_PER_BLOCK 4
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`define NUM_BARRIERS 4
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`define R_INST 7'd51
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`define L_INST 7'd3
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`define ALU_INST 7'd19
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`define S_INST 7'd35
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`define B_INST 7'd99
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`define LUI_INST 7'd55
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`define AUIPC_INST 7'd23
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`define JAL_INST 7'd111
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`define JALR_INST 7'd103
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`define SYS_INST 7'd115
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`define GPGPU_INST 7'h6b
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`define WB_ALU 2'h1
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`define WB_MEM 2'h2
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`define WB_JAL 2'h3
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`define NO_WB 2'h0
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`define RS2_IMMED 1
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`define RS2_REG 0
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`define NO_MEM_READ 3'h7
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`define LB_MEM_READ 3'h0
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`define LH_MEM_READ 3'h1
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`define LW_MEM_READ 3'h2
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`define LBU_MEM_READ 3'h4
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`define LHU_MEM_READ 3'h5
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`define NO_MEM_WRITE 3'h7
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`define SB_MEM_WRITE 3'h0
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`define SH_MEM_WRITE 3'h1
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`define SW_MEM_WRITE 3'h2
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`define NO_BRANCH 3'h0
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`define BEQ 3'h1
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`define BNE 3'h2
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`define BLT 3'h3
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`define BGT 3'h4
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`define BLTU 3'h5
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`define BGTU 3'h6
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`define NO_ALU 5'd15
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`define ADD 5'd0
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`define SUB 5'd1
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`define SLLA 5'd2
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`define SLT 5'd3
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`define SLTU 5'd4
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`define XOR 5'd5
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`define SRL 5'd6
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`define SRA 5'd7
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`define OR 5'd8
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`define AND 5'd9
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`define SUBU 5'd10
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`define LUI_ALU 5'd11
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`define AUIPC_ALU 5'd12
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`define CSR_ALU_RW 5'd13
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`define CSR_ALU_RS 5'd14
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`define CSR_ALU_RC 5'd15
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`define MUL 5'd16
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`define MULH 5'd17
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`define MULHSU 5'd18
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`define MULHU 5'd19
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`define DIV 5'd20
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`define DIVU 5'd21
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`define REM 5'd22
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`define REMU 5'd23
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// WRITEBACK
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`define WB_ALU 2'h1
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`define WB_MEM 2'h2
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`define WB_JAL 2'h3
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`define NO_WB 2'h0
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// JAL
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`define JUMP 1'h1
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`define NO_JUMP 1'h0
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// STALLS
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`define STALL 1'h1
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`define NO_STALL 1'h0
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`define TAKEN 1'b1
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`define NOT_TAKEN 1'b0
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`define ZERO_REG 5'h0
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// `define PARAM
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//Cache configurations
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`define DCACHE_SIZE 4096 //Bytes
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`ifdef SYN
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`define DCACHE_WAYS 1
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`else
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`define DCACHE_WAYS 2
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`endif
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`define DCACHE_BLOCK 128 //Bytes
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`define DCACHE_BANKS 8
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`define DCACHE_NUM_WORDS_PER_BLOCK 4
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`define DCACHE_NUM_REQ `NT
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`define DCACHE_WAY_INDEX $clog2(`DCACHE_WAYS) //set this to 1 if CACHE_WAYS is 1
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//`define DCACHE_WAY_INDEX 1
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`define DCACHE_BLOCK_PER_BANK (`DCACHE_BLOCK / `DCACHE_BANKS)
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// Offset
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`define DCACHE_OFFSET_NB ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK))
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`define DCACHE_OFFSET_ST (2+$clog2(`DCACHE_NUMBER_BANKS))
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`define DCACHE_OFFSET_ED (`DCACHE_OFFSET_ST+(`DCACHE_OFFSET_NB)-1)
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`define DCACHE_ADDR_OFFSET_RNG `DCACHE_OFFSET_ED:`DCACHE_OFFSET_ST
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`define DCACHE_OFFSET_SIZE_RNG ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK)-1):0
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// Index
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`define DCACHE_NUM_IND (`DCACHE_SIZE / (`DCACHE_WAYS * `DCACHE_BLOCK_PER_BANK))
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`define DCACHE_IND_NB ($clog2(`DCACHE_NUM_IND))
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`define DCACHE_IND_ST (`DCACHE_OFFSET_ED+1)
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`define DCACHE_IND_ED (`DCACHE_IND_ST+`DCACHE_IND_NB-1)
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`define DCACHE_ADDR_IND_RNG `DCACHE_IND_ED:`DCACHE_IND_ST
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`define DCACHE_IND_SIZE_RNG `DCACHE_IND_NB-1:0
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// Tag
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`define DCACHE_ADDR_TAG_RNG 31:(`DCACHE_IND_ED+1)
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`define DCACHE_TAG_SIZE_RNG (32-(`DCACHE_IND_ED+1)-1):0
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