35 lines
996 B
Verilog
35 lines
996 B
Verilog
`include "VX_tex_define.vh"
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module VX_tex_lerp #(
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) (
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input wire [`BLEND_FRAC-1:0] blend,
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input wire [31:0] in1,
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input wire [31:0] in2,
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output wire [31:0] out
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);
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wire [63:0] in1_w, in2_w;
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wire [63:0] lerp1, lerp2;
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`UNUSED_VAR (lerp1)
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`UNUSED_VAR (lerp2)
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assign in1_w[15:00] = {8'h00, in1[07:00]};
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assign in1_w[31:16] = {8'h00, in1[15:08]};
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assign in1_w[47:32] = {8'h00, in1[23:16]};
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assign in1_w[63:48] = {8'h00, in1[31:24]};
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assign in2_w[15:00] = {8'h00, in2[07:00]};
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assign in2_w[31:16] = {8'h00, in2[15:08]};
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assign in2_w[47:32] = {8'h00, in2[23:16]};
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assign in2_w[63:48] = {8'h00, in2[31:24]};
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assign lerp1 = (in2_w - in1_w) * blend;
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assign lerp2 = in1_w + {8'h00,lerp1[63:56], 8'h00,lerp1[47:40], 8'h00,lerp1[31:24], 8'h00,lerp1[15:8]};
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assign out[07:00] = lerp2[07:00];
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assign out[15:08] = lerp2[23:16];
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assign out[23:16] = lerp2[39:32];
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assign out[31:24] = lerp2[55:48];
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endmodule |