36 lines
732 B
Systemverilog
36 lines
732 B
Systemverilog
`include "VX_fpu_define.vh"
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module VX_tensor_dpu #(
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) (
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input clk,
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input reset,
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input valid_in,
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input [3:0][1:0][31:0] A_tile,
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input [1:0][3:0][31:0] B_tile,
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input [3:0][3:0][31:0] C_tile,
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output valid_out,
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output [3:0][3:0][31:0] D_tile
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);
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logic [3:0][3:0][31:0] result_hmma;
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always @(*) begin
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dpi_hmma(valid_in, A_tile, B_tile, C_tile, result_hmma);
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end
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VX_shift_register #(
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.DATAW (1 + $bits(D_tile)),
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.DEPTH (`LATENCY_HMMA),
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.RESETW (1)
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) shift_reg (
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.clk (clk),
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.reset (reset),
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.enable (1'b1),
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.data_in ({valid_in, result_hmma}),
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.data_out ({valid_out, D_tile})
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);
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endmodule
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