c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
553 lines
20 KiB
Systemverilog
553 lines
20 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`include "VX_trace.vh"
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`ifdef EXT_F_ENABLE
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`define USED_IREG(x) \
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x``_r = {1'b0, ``x}; \
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use_``x = 1
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`define USED_FREG(x) \
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x``_r = {1'b1, ``x}; \
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use_``x = 1
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`else
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`define USED_IREG(x) \
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x``_r = ``x; \
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use_``x = 1
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`endif
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module VX_decode #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_fetch_if.slave fetch_if,
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// outputs
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VX_decode_if.master decode_if,
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VX_decode_sched_if.master decode_sched_if
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);
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localparam DATAW = `UUID_WIDTH + `NW_WIDTH + `NUM_THREADS + `XLEN + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + (`NR_BITS * 4) + `XLEN + 1 + 1;
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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reg [`EX_BITS-1:0] ex_type;
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reg [`INST_OP_BITS-1:0] op_type;
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reg [`INST_MOD_BITS-1:0] op_mod;
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reg [`NR_BITS-1:0] rd_r, rs1_r, rs2_r, rs3_r;
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reg [`XLEN-1:0] imm;
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reg use_rd, use_rs1, use_rs2, use_rs3, use_PC, use_imm;
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reg is_wstall;
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wire [31:0] instr = fetch_if.data.instr;
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wire [6:0] opcode = instr[6:0];
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wire [1:0] func2 = instr[26:25];
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wire [2:0] func3 = instr[14:12];
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wire [4:0] func5 = instr[31:27];
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wire [6:0] func7 = instr[31:25];
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wire [11:0] u_12 = instr[31:20];
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wire [4:0] rd = instr[11:7];
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wire [4:0] rs1 = instr[19:15];
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wire [4:0] rs2 = instr[24:20];
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wire [4:0] rs3 = instr[31:27];
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`UNUSED_VAR (func2)
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`UNUSED_VAR (func5)
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`UNUSED_VAR (rs3)
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`UNUSED_VAR (use_rd)
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`UNUSED_VAR (use_rs1)
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`UNUSED_VAR (use_rs2)
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`UNUSED_VAR (use_rs3)
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wire is_itype_sh = func3[0] && ~func3[1];
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wire [19:0] ui_imm = instr[31:12];
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`ifdef XLEN_64
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wire [11:0] i_imm = is_itype_sh ? {6'b0, instr[25:20]} : u_12;
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wire [11:0] iw_imm = is_itype_sh ? {7'b0, instr[24:20]} : u_12;
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`else
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wire [11:0] i_imm = is_itype_sh ? {7'b0, instr[24:20]} : u_12;
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`endif
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wire [11:0] s_imm = {func7, rd};
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wire [12:0] b_imm = {instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
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wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
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reg [`INST_ALU_BITS-1:0] r_type;
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always @(*) begin
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case (func3)
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3'h0: r_type = (opcode[5] && func7[5]) ? `INST_ALU_SUB : `INST_ALU_ADD;
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3'h1: r_type = `INST_ALU_SLL;
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3'h2: r_type = `INST_ALU_SLT;
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3'h3: r_type = `INST_ALU_SLTU;
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3'h4: r_type = `INST_ALU_XOR;
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3'h5: r_type = func7[5] ? `INST_ALU_SRA : `INST_ALU_SRL;
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3'h6: r_type = `INST_ALU_OR;
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3'h7: r_type = `INST_ALU_AND;
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endcase
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end
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reg [`INST_BR_BITS-1:0] b_type;
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always @(*) begin
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case (func3)
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3'h0: b_type = `INST_BR_EQ;
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3'h1: b_type = `INST_BR_NE;
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3'h4: b_type = `INST_BR_LT;
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3'h5: b_type = `INST_BR_GE;
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3'h6: b_type = `INST_BR_LTU;
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3'h7: b_type = `INST_BR_GEU;
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default: b_type = 'x;
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endcase
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end
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reg [`INST_BR_BITS-1:0] s_type;
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always @(*) begin
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case (u_12)
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12'h000: s_type = `INST_OP_BITS'(`INST_BR_ECALL);
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12'h001: s_type = `INST_OP_BITS'(`INST_BR_EBREAK);
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12'h002: s_type = `INST_OP_BITS'(`INST_BR_URET);
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12'h102: s_type = `INST_OP_BITS'(`INST_BR_SRET);
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12'h302: s_type = `INST_OP_BITS'(`INST_BR_MRET);
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default: s_type = 'x;
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endcase
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end
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`ifdef EXT_M_ENABLE
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reg [`INST_M_BITS-1:0] m_type;
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always @(*) begin
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case (func3)
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3'h0: m_type = `INST_M_MUL;
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3'h1: m_type = `INST_M_MULH;
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3'h2: m_type = `INST_M_MULHSU;
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3'h3: m_type = `INST_M_MULHU;
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3'h4: m_type = `INST_M_DIV;
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3'h5: m_type = `INST_M_DIVU;
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3'h6: m_type = `INST_M_REM;
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3'h7: m_type = `INST_M_REMU;
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endcase
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end
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`endif
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always @(*) begin
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ex_type = '0;
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op_type = 'x;
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op_mod = '0;
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rd_r = '0;
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rs1_r = '0;
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rs2_r = '0;
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rs3_r = '0;
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imm = 'x;
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use_imm = 0;
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use_PC = 0;
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use_rd = 0;
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use_rs1 = 0;
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use_rs2 = 0;
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use_rs3 = 0;
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is_wstall = 0;
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case (opcode)
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`INST_I: begin
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(r_type);
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use_rd = 1;
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use_imm = 1;
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imm = {{(`XLEN-12){i_imm[11]}}, i_imm};
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`USED_IREG (rd);
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`USED_IREG (rs1);
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end
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`INST_R: begin
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ex_type = `EX_ALU;
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`ifdef EXT_M_ENABLE
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if (func7[0]) begin
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op_type = `INST_OP_BITS'(m_type);
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op_mod[1] = 1;
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end else
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`endif
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begin
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op_type = `INST_OP_BITS'(r_type);
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end
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use_rd = 1;
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`USED_IREG (rd);
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`USED_IREG (rs1);
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`USED_IREG (rs2);
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end
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`ifdef XLEN_64
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`INST_I_W: begin
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// ADDIW, SLLIW, SRLIW, SRAIW
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(r_type);
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op_mod[2] = 1;
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use_rd = 1;
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use_imm = 1;
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imm = {{(`XLEN-12){iw_imm[11]}}, iw_imm};
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`USED_IREG (rd);
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`USED_IREG (rs1);
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end
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`INST_R_W: begin
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ex_type = `EX_ALU;
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`ifdef EXT_M_ENABLE
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if (func7[0]) begin
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// MULW, DIVW, DIVUW, REMW, REMUW
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op_type = `INST_OP_BITS'(m_type);
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op_mod[1] = 1;
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end else
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`endif
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begin
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// ADDW, SUBW, SLLW, SRLW, SRAW
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op_type = `INST_OP_BITS'(r_type);
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end
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op_mod[2] = 1;
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use_rd = 1;
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`USED_IREG (rd);
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`USED_IREG (rs1);
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`USED_IREG (rs2);
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end
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`endif
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`INST_LUI: begin
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(`INST_ALU_LUI);
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use_rd = 1;
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use_imm = 1;
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imm = {{`XLEN-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)};
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`USED_IREG (rd);
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end
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`INST_AUIPC: begin
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(`INST_ALU_AUIPC);
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use_rd = 1;
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use_imm = 1;
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use_PC = 1;
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imm = {{`XLEN-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)};
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`USED_IREG (rd);
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end
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`INST_JAL: begin
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(`INST_BR_JAL);
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op_mod[0] = 1;
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use_rd = 1;
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use_imm = 1;
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use_PC = 1;
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is_wstall = 1;
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imm = {{(`XLEN-21){jal_imm[20]}}, jal_imm};
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`USED_IREG (rd);
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end
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`INST_JALR: begin
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(`INST_BR_JALR);
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op_mod[0] = 1;
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use_rd = 1;
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use_imm = 1;
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is_wstall = 1;
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imm = {{(`XLEN-12){u_12[11]}}, u_12};
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`USED_IREG (rd);
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`USED_IREG (rs1);
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end
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`INST_B: begin
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(b_type);
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op_mod[0] = 1;
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use_imm = 1;
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use_PC = 1;
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is_wstall = 1;
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imm = {{(`XLEN-13){b_imm[12]}}, b_imm};
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`USED_IREG (rs1);
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`USED_IREG (rs2);
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end
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`INST_FENCE: begin
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ex_type = `EX_LSU;
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op_type = `INST_LSU_FENCE;
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end
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`INST_SYS : begin
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if (func3[1:0] != 0) begin
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ex_type = `EX_SFU;
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op_type = `INST_OP_BITS'(`INST_SFU_CSR(func3[1:0]));
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use_rd = 1;
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is_wstall = 1;
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use_imm = func3[2];
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imm[`VX_CSR_ADDR_BITS-1:0] = u_12; // addr
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`USED_IREG (rd);
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if (func3[2]) begin
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imm[`VX_CSR_ADDR_BITS +: `NRI_BITS] = rs1; // imm
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end else begin
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`USED_IREG (rs1);
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end
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end else begin
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ex_type = `EX_ALU;
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op_type = `INST_OP_BITS'(s_type);
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op_mod[0] = 1;
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use_rd = 1;
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use_imm = 1;
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use_PC = 1;
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is_wstall = 1;
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imm = `XLEN'd4;
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`USED_IREG (rd);
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end
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end
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`ifdef EXT_F_ENABLE
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`INST_FL,
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`endif
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`INST_L: begin
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ex_type = `EX_LSU;
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op_type = `INST_OP_BITS'({1'b0, func3});
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use_rd = 1;
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imm = {{(`XLEN-12){u_12[11]}}, u_12};
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use_imm = 1;
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`ifdef EXT_F_ENABLE
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if (opcode[2]) begin
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`USED_FREG (rd);
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end else
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`endif
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`USED_IREG (rd);
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`USED_IREG (rs1);
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end
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`ifdef EXT_F_ENABLE
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`INST_FS,
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`endif
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`INST_S: begin
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ex_type = `EX_LSU;
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op_type = `INST_OP_BITS'({1'b1, func3});
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imm = {{(`XLEN-12){s_imm[11]}}, s_imm};
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use_imm = 1;
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`USED_IREG (rs1);
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`ifdef EXT_F_ENABLE
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if (opcode[2]) begin
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`USED_FREG (rs2);
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end else
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`endif
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`USED_IREG (rs2);
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end
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`ifdef EXT_F_ENABLE
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`INST_FMADD,
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`INST_FMSUB,
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`INST_FNMSUB,
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`INST_FNMADD: begin
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ex_type = `EX_FPU;
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op_type = `INST_OP_BITS'({2'b11, opcode[3:2]});
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op_mod = `INST_MOD_BITS'(func3);
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imm[0] = func2[0]; // destination is double?
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use_rd = 1;
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`USED_FREG (rd);
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`USED_FREG (rs1);
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`USED_FREG (rs2);
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`USED_FREG (rs3);
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end
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`INST_FCI: begin
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ex_type = `EX_FPU;
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op_mod = `INST_MOD_BITS'(func3);
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`ifdef FLEN_64
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imm[0] = func2[0]; // destination is double?
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`endif
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use_rd = 1;
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case (func5)
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5'b00000, // FADD
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5'b00001, // FSUB
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5'b00010, // FMUL
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5'b00011: begin // FDIV
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op_type = `INST_OP_BITS'(func5[1:0]);
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`USED_FREG (rd);
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`USED_FREG (rs1);
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`USED_FREG (rs2);
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end
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5'b00100: begin
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// NCP: FSGNJ=0, FSGNJN=1, FSGNJX=2
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op_type = `INST_OP_BITS'(`INST_FPU_MISC);
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op_mod = `INST_MOD_BITS'(func3[1:0]);
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`USED_FREG (rd);
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`USED_FREG (rs1);
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`USED_FREG (rs2);
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end
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5'b00101: begin
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// NCP: FMIN=6, FMAX=7
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op_type = `INST_OP_BITS'(`INST_FPU_MISC);
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op_mod = func3[0] ? 7 : 6;
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`USED_FREG (rd);
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`USED_FREG (rs1);
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`USED_FREG (rs2);
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end
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`ifdef FLEN_64
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5'b01000: begin
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// CVT.S.D, CVT.D.S
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op_type = `INST_OP_BITS'(`INST_FPU_F2F);
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`USED_FREG (rd);
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`USED_FREG (rs1);
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end
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`endif
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5'b01011: begin
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// SQRT
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op_type = `INST_OP_BITS'(`INST_FPU_SQRT);
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`USED_FREG (rd);
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`USED_FREG (rs1);
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end
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5'b10100: begin
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// CMP
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op_type = `INST_OP_BITS'(`INST_FPU_CMP);
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`USED_IREG (rd);
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`USED_FREG (rs1);
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`USED_FREG (rs2);
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end
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5'b11000: begin
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// CVT.W.X, CVT.WU.X
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op_type = (rs2[0]) ? `INST_OP_BITS'(`INST_FPU_F2U) : `INST_OP_BITS'(`INST_FPU_F2I);
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`ifdef XLEN_64
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imm[1] = rs2[1]; // is 64-bit integer
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`endif
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`USED_IREG (rd);
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`USED_FREG (rs1);
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end
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5'b11010: begin
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// CVT.X.W, CVT.X.WU
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op_type = (rs2[0]) ? `INST_OP_BITS'(`INST_FPU_U2F) : `INST_OP_BITS'(`INST_FPU_I2F);
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`ifdef XLEN_64
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imm[1] = rs2[1]; // is 64-bit integer
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`endif
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`USED_FREG (rd);
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`USED_IREG (rs1);
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end
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5'b11100: begin
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if (func3[0]) begin
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// NCP: FCLASS=3
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op_type = `INST_OP_BITS'(`INST_FPU_MISC);
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op_mod = 3;
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end else begin
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// NCP: FMV.X.W=4
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op_type = `INST_OP_BITS'(`INST_FPU_MISC);
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op_mod = 4;
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end
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`USED_IREG (rd);
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`USED_FREG (rs1);
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end
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5'b11110: begin
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// NCP: FMV.W.X=5
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op_type = `INST_OP_BITS'(`INST_FPU_MISC);
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op_mod = 5;
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`USED_FREG (rd);
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`USED_IREG (rs1);
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end
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default:;
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endcase
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end
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`endif
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`INST_EXT1: begin
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case (func7)
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7'h00: begin
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ex_type = `EX_SFU;
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is_wstall = 1;
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case (func3)
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3'h0: begin // TMC
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op_type = `INST_OP_BITS'(`INST_SFU_TMC);
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`USED_IREG (rs1);
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end
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3'h1: begin // WSPAWN
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op_type = `INST_OP_BITS'(`INST_SFU_WSPAWN);
|
|
`USED_IREG (rs1);
|
|
`USED_IREG (rs2);
|
|
end
|
|
3'h2: begin // SPLIT
|
|
op_type = `INST_OP_BITS'(`INST_SFU_SPLIT);
|
|
use_rd = 1;
|
|
`USED_IREG (rs1);
|
|
`USED_IREG (rd);
|
|
end
|
|
3'h3: begin // JOIN
|
|
op_type = `INST_OP_BITS'(`INST_SFU_JOIN);
|
|
`USED_IREG (rs1);
|
|
end
|
|
3'h4: begin // BAR
|
|
op_type = `INST_OP_BITS'(`INST_SFU_BAR);
|
|
`USED_IREG (rs1);
|
|
`USED_IREG (rs2);
|
|
end
|
|
3'h5: begin // PRED
|
|
op_type = `INST_OP_BITS'(`INST_SFU_PRED);
|
|
`USED_IREG (rs1);
|
|
`USED_IREG (rs2);
|
|
end
|
|
default:;
|
|
endcase
|
|
end
|
|
default:;
|
|
endcase
|
|
end
|
|
`INST_EXT2: begin
|
|
case (func3)
|
|
3'h1: begin
|
|
case (func2)
|
|
2'h0: begin // CMOV
|
|
ex_type = `EX_SFU;
|
|
op_type = `INST_OP_BITS'(`INST_SFU_CMOV);
|
|
use_rd = 1;
|
|
`USED_IREG (rd);
|
|
`USED_IREG (rs1);
|
|
`USED_IREG (rs2);
|
|
`USED_IREG (rs3);
|
|
end
|
|
default:;
|
|
endcase
|
|
end
|
|
default:;
|
|
endcase
|
|
end
|
|
default:;
|
|
endcase
|
|
end
|
|
|
|
// disable write to integer register r0
|
|
wire wb = use_rd && (rd_r != 0);
|
|
|
|
VX_elastic_buffer #(
|
|
.DATAW (DATAW),
|
|
.SIZE (0)
|
|
) req_buf (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.valid_in (fetch_if.valid),
|
|
.ready_in (fetch_if.ready),
|
|
.data_in ({fetch_if.data.uuid, fetch_if.data.wid, fetch_if.data.tmask, fetch_if.data.PC, ex_type, op_type, op_mod, use_PC, imm, use_imm, wb, rd_r, rs1_r, rs2_r, rs3_r}),
|
|
.data_out ({decode_if.data.uuid, decode_if.data.wid, decode_if.data.tmask, decode_if.data.PC, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod, decode_if.data.use_PC, decode_if.data.imm, decode_if.data.use_imm, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3}),
|
|
.valid_out (decode_if.valid),
|
|
.ready_out (decode_if.ready)
|
|
);
|
|
|
|
///////////////////////////////////////////////////////////////////////////
|
|
|
|
wire fetch_fire = fetch_if.valid && fetch_if.ready;
|
|
|
|
assign decode_sched_if.valid = fetch_fire;
|
|
assign decode_sched_if.wid = fetch_if.data.wid;
|
|
assign decode_sched_if.is_wstall = is_wstall;
|
|
|
|
assign fetch_if.ibuf_pop = decode_if.ibuf_pop;
|
|
|
|
`ifdef DBG_TRACE_CORE_PIPELINE
|
|
always @(posedge clk) begin
|
|
if (decode_if.valid && decode_if.ready) begin
|
|
`TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, instr=0x%0h, ex=", $time, CORE_ID, decode_if.data.wid, decode_if.data.PC, instr));
|
|
trace_ex_type(1, decode_if.data.ex_type);
|
|
`TRACE(1, (", op="));
|
|
trace_ex_op(1, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod, decode_if.data.rd, decode_if.data.rs2, decode_if.data.use_imm, decode_if.data.imm);
|
|
`TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=0x%0h, opds=%b%b%b%b, use_pc=%b, use_imm=%b (#%0d)\n",
|
|
decode_if.data.op_mod, decode_if.data.tmask, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3, decode_if.data.imm, use_rd, use_rs1, use_rs2, use_rs3, decode_if.data.use_PC, decode_if.data.use_imm, decode_if.data.uuid));
|
|
end
|
|
end
|
|
`endif
|
|
|
|
endmodule
|