432 lines
22 KiB
Verilog
432 lines
22 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_cache #(
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// Size of cache in bytes
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parameter CACHE_SIZE_BYTES = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE_BYTES = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE_BYTES = 16,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUM_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
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parameter FUNC_ID = 3,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Forward SNP Queue
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parameter FFSQ_SIZE = 8,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// Prefetcher
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parameter PRFQ_SIZE = 64,
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parameter PRFQ_STRIDE = 0,
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// Dram knobs
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parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
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) (
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input wire clk,
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input wire reset,
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// Core request
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input wire [NUM_REQUESTS-1:0] core_req_valid,
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input wire [NUM_REQUESTS-1:0][2:0] core_req_read,
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input wire [NUM_REQUESTS-1:0][2:0] core_req_write,
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input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
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input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_data,
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output wire core_req_ready,
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// Core request meta data
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input wire [4:0] core_req_rd,
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input wire [NUM_REQUESTS-1:0][1:0] core_req_wb,
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input wire [`NW_BITS-1:0] core_req_warp_num,
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input wire [31:0] core_req_pc,
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// Core response
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output wire [NUM_REQUESTS-1:0] core_rsp_valid,
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output wire [4:0] core_rsp_read,
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output wire [1:0] core_rsp_write,
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output wire [NUM_REQUESTS-1:0][31:0] core_rsp_addr,
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output wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_data,
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input wire core_rsp_ready,
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// Core response meta data
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output wire [`NW_BITS-1:0] core_rsp_warp_num,
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output wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc,
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// DRAM request
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output wire dram_req_read,
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output wire dram_req_write,
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output wire [31:0] dram_req_addr,
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output wire [`IBANK_LINE_WORDS-1:0][31:0] dram_req_data,
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input wire dram_req_ready,
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// DRAM response
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input wire dram_rsp_valid,
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input wire [31:0] dram_rsp_addr,
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input wire [`IBANK_LINE_WORDS-1:0][31:0] dram_rsp_data,
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output wire dram_rsp_ready,
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// Snoop Req
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input wire snp_req_valid,
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input wire [31:0] snp_req_addr,
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output wire snp_req_ready,
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// Snoop Forward
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output wire snp_fwd_valid,
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output wire [31:0] snp_fwd_addr,
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input wire snp_fwd_ready
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);
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wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_pop;
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wire [NUM_BANKS-1:0] per_bank_core_rsp_valid;
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wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_core_rsp_tid;
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wire [NUM_BANKS-1:0][4:0] per_bank_core_rsp_rd;
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wire [NUM_BANKS-1:0][1:0] per_bank_core_rsp_wb;
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wire [NUM_BANKS-1:0][`NW_BITS-1:0] per_bank_core_rsp_warp_num;
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wire [NUM_BANKS-1:0][`WORD_SIZE_RNG] per_bank_core_rsp_data;
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wire [NUM_BANKS-1:0][31:0] per_bank_core_rsp_pc;
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wire [NUM_BANKS-1:0][31:0] per_bank_core_rsp_addr;
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wire dfqq_full;
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wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid;
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wire [NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
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`DEBUG_BEGIN
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wire [NUM_BANKS-1:0] per_bank_dram_fill_req_is_snp;
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`DEBUG_END
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wire [NUM_BANKS-1:0] per_bank_dram_fill_rsp_ready;
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wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop;
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wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid;
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wire [NUM_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
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wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data;
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wire [NUM_BANKS-1:0] per_bank_reqq_full;
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wire [NUM_BANKS-1:0] per_bank_snp_req_full;
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wire [NUM_BANKS-1:0] per_bank_snp_fwd_valid;
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wire [NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr;
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wire [NUM_BANKS-1:0] per_bank_snp_fwd_pop;
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assign core_req_ready = ~(|per_bank_reqq_full);
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assign snp_req_ready = ~(|per_bank_snp_req_full);
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// assign dram_rsp_ready = (NUM_BANKS == 1) ? per_bank_dram_fill_rsp_ready[0] : per_bank_dram_fill_rsp_ready[dram_rsp_addr[`BANK_SELECT_ADDR_RNG]];
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assign dram_rsp_ready = (|per_bank_dram_fill_rsp_ready);
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VX_cache_dram_req_arb #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.PRFQ_SIZE (PRFQ_SIZE),
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.PRFQ_STRIDE (PRFQ_STRIDE),
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.SIMULATED_DRAM_LATENCY_CYCLES (SIMULATED_DRAM_LATENCY_CYCLES)
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) cache_dram_req_arb (
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.clk (clk),
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.reset (reset),
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.dfqq_full (dfqq_full),
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.per_bank_dram_fill_req_valid (per_bank_dram_fill_req_valid),
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.per_bank_dram_fill_req_addr (per_bank_dram_fill_req_addr),
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.per_bank_dram_wb_queue_pop (per_bank_dram_wb_queue_pop),
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.per_bank_dram_wb_req_valid (per_bank_dram_wb_req_valid),
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.per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr),
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.per_bank_dram_wb_req_data (per_bank_dram_wb_req_data),
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.dram_req_read (dram_req_read),
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.dram_req_write (dram_req_write),
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.dram_req_addr (dram_req_addr),
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.dram_req_data (dram_req_data),
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.dram_req_ready (dram_req_ready)
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);
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VX_cache_core_req_bank_sel #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.SIMULATED_DRAM_LATENCY_CYCLES (SIMULATED_DRAM_LATENCY_CYCLES)
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) cache_core_req_bank_sell (
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.core_req_valid (core_req_valid),
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.core_req_addr (core_req_addr),
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.per_bank_valids (per_bank_valids)
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);
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VX_cache_wb_sel_merge #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.FUNC_ID (FUNC_ID),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
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) cache_core_rsp_sel_merge (
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.per_bank_wb_valid (per_bank_core_rsp_valid),
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.per_bank_wb_tid (per_bank_core_rsp_tid),
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.per_bank_wb_rd (per_bank_core_rsp_rd),
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.per_bank_wb_pc (per_bank_core_rsp_pc),
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.per_bank_wb_wb (per_bank_core_rsp_wb),
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.per_bank_wb_warp_num(per_bank_core_rsp_warp_num),
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.per_bank_wb_data (per_bank_core_rsp_data),
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.per_bank_wb_pop (per_bank_core_rsp_pop),
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.per_bank_wb_addr (per_bank_core_rsp_addr),
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.core_rsp_ready (core_rsp_ready),
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.core_rsp_valid (core_rsp_valid),
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.core_rsp_read (core_rsp_read),
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.core_rsp_write (core_rsp_write),
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.core_rsp_warp_num (core_rsp_warp_num),
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.core_rsp_data (core_rsp_data),
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.core_rsp_addr (core_rsp_addr),
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.core_rsp_pc (core_rsp_pc)
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);
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// Snoop Forward Logic
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VX_snp_fwd_arb #(
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.NUM_BANKS(NUM_BANKS)
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) snp_fwd_arb (
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.per_bank_snp_fwd_valid (per_bank_snp_fwd_valid),
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.per_bank_snp_fwd_addr (per_bank_snp_fwd_addr),
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.per_bank_snp_fwd_pop (per_bank_snp_fwd_pop),
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.snp_fwd_valid (snp_fwd_valid),
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.snp_fwd_addr (snp_fwd_addr),
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.snp_fwd_ready (snp_fwd_ready)
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);
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// Snoop Forward Logic
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genvar curr_bank;
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generate
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for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank=curr_bank+1) begin
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wire [NUM_REQUESTS-1:0] curr_bank_core_req_valids;
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wire [NUM_REQUESTS-1:0][31:0] curr_bank_core_req_addr;
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wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_core_req_data;
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wire [4:0] curr_bank_core_req_rd;
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wire [NUM_REQUESTS-1:0][1:0] curr_bank_core_req_wb;
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wire [`NW_BITS-1:0] curr_bank_core_warp_num;
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wire [NUM_REQUESTS-1:0][2:0] curr_bank_core_req_read;
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wire [NUM_REQUESTS-1:0][2:0] curr_bank_core_req_write;
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wire [31:0] curr_bank_core_req_pc;
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wire curr_bank_core_rsp_pop;
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wire curr_bank_core_rsp_valid;
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wire [`LOG2UP(NUM_REQUESTS)-1:0] curr_bank_core_rsp_tid;
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wire [31:0] curr_bank_core_rsp_pc;
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wire [4:0] curr_bank_core_rsp_rd;
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wire [1:0] curr_bank_core_rsp_wb;
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wire [`NW_BITS-1:0] curr_bank_core_rsp_warp_num;
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wire [`WORD_SIZE_RNG] curr_bank_core_rsp_data;
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wire [31:0] curr_bank_core_rsp_addr;
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wire curr_bank_dram_fill_rsp_valid;
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wire [31:0] curr_bank_dram_fill_rsp_addr;
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wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data;
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wire curr_bank_dram_fill_rsp_ready;
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wire curr_bank_dram_fill_req_full;
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wire curr_bank_dram_fill_req_valid;
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wire curr_bank_dram_fill_req_is_snp;
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wire[31:0] curr_bank_dram_fill_req_addr;
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wire curr_bank_dram_wb_req_pop;
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wire curr_bank_dram_wb_req_valid;
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wire[31:0] curr_bank_dram_wb_req_addr;
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wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_wb_req_data;
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wire curr_bank_snp_req;
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wire[31:0] curr_bank_snp_req_addr;
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wire curr_bank_reqq_full;
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wire curr_bank_snp_fwd_valid;
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wire[31:0] curr_bank_snp_fwd_addr;
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wire curr_bank_snp_fwd_pop;
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wire curr_bank_snp_req_full;
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// Core Req
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assign curr_bank_core_req_valids = per_bank_valids[curr_bank];
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assign curr_bank_core_req_addr = core_req_addr;
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assign curr_bank_core_req_data = core_req_data;
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assign curr_bank_core_req_rd = core_req_rd;
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assign curr_bank_core_req_wb = core_req_wb;
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assign curr_bank_core_req_pc = core_req_pc;
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assign curr_bank_core_warp_num = core_req_warp_num;
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assign curr_bank_core_req_read = core_req_read;
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assign curr_bank_core_req_write = core_req_write;
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assign per_bank_reqq_full[curr_bank] = curr_bank_reqq_full;
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// Core WB
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assign curr_bank_core_rsp_pop = per_bank_core_rsp_pop[curr_bank];
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assign per_bank_core_rsp_valid [curr_bank] = curr_bank_core_rsp_valid;
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assign per_bank_core_rsp_tid [curr_bank] = curr_bank_core_rsp_tid;
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assign per_bank_core_rsp_rd [curr_bank] = curr_bank_core_rsp_rd;
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assign per_bank_core_rsp_wb [curr_bank] = curr_bank_core_rsp_wb;
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assign per_bank_core_rsp_warp_num[curr_bank] = curr_bank_core_rsp_warp_num;
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assign per_bank_core_rsp_data [curr_bank] = curr_bank_core_rsp_data;
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assign per_bank_core_rsp_pc [curr_bank] = curr_bank_core_rsp_pc;
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assign per_bank_core_rsp_addr [curr_bank] = curr_bank_core_rsp_addr;
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// Dram fill request
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assign curr_bank_dram_fill_req_full = dfqq_full;
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assign per_bank_dram_fill_req_valid[curr_bank] = curr_bank_dram_fill_req_valid;
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assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr;
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assign per_bank_dram_fill_req_is_snp[curr_bank] = curr_bank_dram_fill_req_is_snp;
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// Dram fill response
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assign curr_bank_dram_fill_rsp_valid = (NUM_BANKS == 1) || (dram_rsp_valid && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank));
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assign curr_bank_dram_fill_rsp_addr = dram_rsp_addr;
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assign curr_bank_dram_fill_rsp_data = dram_rsp_data;
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assign per_bank_dram_fill_rsp_ready[curr_bank] = curr_bank_dram_fill_rsp_ready;
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// Dram writeback request
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assign curr_bank_dram_wb_req_pop = per_bank_dram_wb_queue_pop[curr_bank];
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assign per_bank_dram_wb_req_valid[curr_bank] = curr_bank_dram_wb_req_valid;
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assign per_bank_dram_wb_req_addr[curr_bank] = curr_bank_dram_wb_req_addr;
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assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data;
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// Snoop Request
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assign curr_bank_snp_req = snp_req_valid && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
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assign curr_bank_snp_req_addr = snp_req_addr;
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assign per_bank_snp_req_full[curr_bank] = curr_bank_snp_req_full;
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// Snoop Fwd
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assign per_bank_snp_fwd_valid[curr_bank] = curr_bank_snp_fwd_valid;
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assign per_bank_snp_fwd_addr[curr_bank] = curr_bank_snp_fwd_addr;
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assign curr_bank_snp_fwd_pop = per_bank_snp_fwd_pop[curr_bank];
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VX_bank #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
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.NUM_REQUESTS (NUM_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.FUNC_ID (FUNC_ID),
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|
.REQQ_SIZE (REQQ_SIZE),
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|
.MRVQ_SIZE (MRVQ_SIZE),
|
|
.DFPQ_SIZE (DFPQ_SIZE),
|
|
.SNRQ_SIZE (SNRQ_SIZE),
|
|
.CWBQ_SIZE (CWBQ_SIZE),
|
|
.DWBQ_SIZE (DWBQ_SIZE),
|
|
.DFQQ_SIZE (DFQQ_SIZE),
|
|
.LLVQ_SIZE (LLVQ_SIZE),
|
|
.FFSQ_SIZE (FFSQ_SIZE),
|
|
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
|
|
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
|
|
) bank (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
// Core request
|
|
.core_req_valids (curr_bank_core_req_valids),
|
|
.core_req_read (curr_bank_core_req_read),
|
|
.core_req_write (curr_bank_core_req_write),
|
|
.core_req_addr (curr_bank_core_req_addr),
|
|
.core_req_data (curr_bank_core_req_data),
|
|
.core_req_rd (curr_bank_core_req_rd),
|
|
.core_req_wb (curr_bank_core_req_wb),
|
|
.core_req_pc (curr_bank_core_req_pc),
|
|
.core_req_warp_num (curr_bank_core_warp_num),
|
|
.core_req_full (curr_bank_reqq_full),
|
|
.core_req_ready (core_req_ready),
|
|
|
|
// Core response
|
|
.core_rsp_valid (curr_bank_core_rsp_valid),
|
|
.core_rsp_tid (curr_bank_core_rsp_tid),
|
|
.core_rsp_rd (curr_bank_core_rsp_rd),
|
|
.core_rsp_wb (curr_bank_core_rsp_wb),
|
|
.core_rsp_warp_num (curr_bank_core_rsp_warp_num),
|
|
.core_rsp_data (curr_bank_core_rsp_data),
|
|
.core_rsp_pc (curr_bank_core_rsp_pc),
|
|
.core_rsp_addr (curr_bank_core_rsp_addr),
|
|
.core_rsp_pop (curr_bank_core_rsp_pop),
|
|
|
|
// Dram fill request
|
|
.dram_fill_req_valid (curr_bank_dram_fill_req_valid),
|
|
.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
|
|
.dram_fill_req_is_snp (curr_bank_dram_fill_req_is_snp),
|
|
.dram_fill_req_full (curr_bank_dram_fill_req_full),
|
|
|
|
// Dram fill response
|
|
.dram_fill_rsp_valid (curr_bank_dram_fill_rsp_valid),
|
|
.dram_fill_rsp_addr (curr_bank_dram_fill_rsp_addr),
|
|
.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
|
|
.dram_fill_rsp_ready (curr_bank_dram_fill_rsp_ready),
|
|
|
|
// Dram writeback request
|
|
.dram_wb_req_valid (curr_bank_dram_wb_req_valid),
|
|
.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
|
|
.dram_wb_req_data (curr_bank_dram_wb_req_data),
|
|
.dram_wb_req_pop (curr_bank_dram_wb_req_pop),
|
|
|
|
// Snoop request
|
|
.snp_req_valid (curr_bank_snp_req),
|
|
.snp_req_addr (curr_bank_snp_req_addr),
|
|
.snp_req_full (curr_bank_snp_req_full),
|
|
|
|
// Snoop forwarding
|
|
.snp_fwd_valid (curr_bank_snp_fwd_valid),
|
|
.snp_fwd_addr (curr_bank_snp_fwd_addr),
|
|
.snp_fwd_pop (curr_bank_snp_fwd_pop)
|
|
);
|
|
end
|
|
|
|
endgenerate
|
|
|
|
endmodule |