138 lines
4.6 KiB
Verilog
138 lines
4.6 KiB
Verilog
`include "VX_tex_define.vh"
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module VX_tex_sampler #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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input wire req_valid,
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input wire [`NW_BITS-1:0] req_wid,
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input wire [`NUM_THREADS-1:0] req_tmask,
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input wire [31:0] req_PC,
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input wire [`NR_BITS-1:0] req_rd,
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input wire req_wb,
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input wire [`TEX_FORMAT_BITS-1:0] req_format,
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input wire [`NUM_THREADS-1:0][3:0][31:0] req_data,
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input wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] req_blend_u,
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input wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] req_blend_v,
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output wire req_ready,
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// ouputs
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output wire rsp_valid,
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output wire [`NW_BITS-1:0] rsp_wid,
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output wire [`NUM_THREADS-1:0] rsp_tmask,
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output wire [31:0] rsp_PC,
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output wire [`NR_BITS-1:0] rsp_rd,
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output wire rsp_wb,
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output wire [`NUM_THREADS-1:0][31:0] rsp_data,
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input wire rsp_ready
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);
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`UNUSED_PARAM (CORE_ID)
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wire [`NUM_THREADS-1:0][31:0] texel_ul, texel_uh;
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wire [`NUM_THREADS-1:0][31:0] texel_ul_s0, texel_uh_s0;
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wire [`NUM_THREADS-1:0][`BLEND_FRAC-1:0] blend_v_s0;
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wire [`NUM_THREADS-1:0][31:0] texel_v;
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wire req_valid_s0;
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wire [`NW_BITS-1:0] req_wid_s0;
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wire [`NUM_THREADS-1:0] req_tmask_s0;
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wire [31:0] req_PC_s0;
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wire [`NR_BITS-1:0] req_rd_s0;
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wire req_wb_s0;
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wire stall_out;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [3:0][31:0] fmt_texels;
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for (genvar j = 0; j < 4; j++) begin
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VX_tex_format #(
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.CORE_ID (CORE_ID)
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) tex_format (
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.format (req_format),
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.texel_in (req_data[i][j]),
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.texel_out (fmt_texels[j])
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);
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end
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VX_tex_lerp #(
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) tex_lerp_ul (
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.blend (req_blend_u[i]),
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.in1 (fmt_texels[0]),
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.in2 (fmt_texels[1]),
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.out (texel_ul[i])
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);
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VX_tex_lerp #(
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) tex_lerp_uh (
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.blend (req_blend_u[i]),
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.in1 (fmt_texels[2]),
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.in2 (fmt_texels[3]),
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.out (texel_uh[i])
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);
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end
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * `BLEND_FRAC) + (2 * `NUM_THREADS * 32)),
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.RESETW (1)
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) pipe_reg0 (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({req_valid, req_wid, req_tmask, req_PC, req_rd, req_wb, req_blend_v, texel_ul, texel_uh}),
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.data_out ({req_valid_s0, req_wid_s0, req_tmask_s0, req_PC_s0, req_rd_s0, req_wb_s0, blend_v_s0, texel_ul_s0, texel_uh_s0})
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);
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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VX_tex_lerp #(
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) tex_lerp_v (
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.blend (blend_v_s0[i]),
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.in1 (texel_ul_s0[i]),
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.in2 (texel_uh_s0[i]),
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.out (texel_v[i])
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);
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end
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assign stall_out = rsp_valid && ~rsp_ready;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
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.RESETW (1)
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) pipe_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({req_valid_s0, req_wid_s0, req_tmask_s0, req_PC_s0, req_rd_s0, req_wb_s0, texel_v}),
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.data_out ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data})
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);
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// can accept new request?
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assign req_ready = ~stall_out;
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`ifdef DBG_PRINT_TEX
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always @(posedge clk) begin
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if (req_valid && req_ready) begin
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$write("%t: core%0d-tex-sampler-req: wid=%0d, PC=%0h, tmask=%b, format=%0d, data=",
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$time, CORE_ID, req_wid, req_PC, req_tmask, req_format);
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`PRINT_ARRAY2D(req_data, 4, `NUM_THREADS);
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$write(", u0=");
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`PRINT_ARRAY1D(req_blend_u, `NUM_THREADS);
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$write(", v0=");
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`PRINT_ARRAY1D(req_blend_v, `NUM_THREADS);
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$write("\n");
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end
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if (rsp_valid && rsp_ready) begin
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$write("%t: core%0d-tex-sampler-rsp: wid=%0d, PC=%0h, tmask=%b, data=",
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$time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask);
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`PRINT_ARRAY1D(rsp_data, `NUM_THREADS);
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$write("\n");
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end
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end
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`endif
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endmodule |