23 lines
467 B
Verilog
23 lines
467 B
Verilog
`ifndef VX_WRITEBACK_IF
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`define VX_WRITEBACK_IF
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`include "VX_define.vh"
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interface VX_writeback_if ();
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wire valid;
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wire [`NUM_THREADS-1:0] tmask;
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wire [`NW_BITS-1:0] wid;
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`IGNORE_WARNINGS_BEGIN
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wire [31:0] PC;
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`IGNORE_WARNINGS_END
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wire [`NR_BITS-1:0] rd;
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wire [`NUM_THREADS-1:0][31:0] data;
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wire ready;
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endinterface
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`endif
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