82 lines
2.9 KiB
Verilog
82 lines
2.9 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_io_arb #(
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parameter NUM_REQS = 1,
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parameter DATA_WIDTH = 1,
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parameter DATA_SIZE = (DATA_WIDTH / 8),
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parameter ADDR_WIDTH = 32 - `CLOG2(DATA_SIZE),
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parameter REQS_BITS = `LOG2UP(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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input wire [REQS_BITS-1:0] request_id,
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// input requests
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input wire csr_io_req_valid_in,
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input wire [ADDR_WIDTH-1:0] csr_io_req_addr_in,
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input wire csr_io_req_rw_in,
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input wire [DATA_WIDTH-1:0] csr_io_req_data_in,
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output wire csr_io_req_ready_in,
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// output request
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output wire [NUM_REQS-1:0] csr_io_req_valid_out,
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output wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] csr_io_req_addr_out,
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output wire [NUM_REQS-1:0] csr_io_req_rw_out,
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output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] csr_io_req_data_out,
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input wire [NUM_REQS-1:0] csr_io_req_ready_out,
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// input response
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input wire [NUM_REQS-1:0] csr_io_rsp_valid_in,
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input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] csr_io_rsp_data_in,
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output wire [NUM_REQS-1:0] csr_io_rsp_ready_in,
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// output response
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output wire csr_io_rsp_valid_out,
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output wire [DATA_WIDTH-1:0] csr_io_rsp_data_out,
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input wire csr_io_rsp_ready_out
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);
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if (NUM_REQS > 1) begin
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign csr_io_req_valid_out[i] = csr_io_req_valid_in && (request_id == `REQS_BITS'(i));
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assign csr_io_req_addr_out[i] = csr_io_req_addr_in;
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assign csr_io_req_rw_out[i] = csr_io_req_rw_in;
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assign csr_io_req_data_out[i] = csr_io_req_data_in;
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end
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assign csr_io_req_ready_in = csr_io_req_ready_out[request_id];
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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`UNUSED_VAR (request_id)
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assign csr_io_req_valid_out = csr_io_req_valid_in;
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assign csr_io_req_addr_out = csr_io_req_addr_in;
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assign csr_io_req_rw_out = csr_io_req_rw_in;
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assign csr_io_req_data_out = csr_io_req_data_in;
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assign csr_io_req_ready_in = csr_io_req_ready_out;
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end
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///////////////////////////////////////////////////////////////////////
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VX_stream_arbiter #(
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.NUM_REQS(NUM_REQS),
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.DATAW(DATA_WIDTH),
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.BUFFERED(NUM_REQS >= 4)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (csr_io_rsp_valid_in),
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.valid_out (csr_io_rsp_valid_out),
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.data_in (csr_io_rsp_data_in),
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.data_out (csr_io_rsp_data_out),
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.ready_in (csr_io_rsp_ready_in),
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.ready_out (csr_io_rsp_ready_out)
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);
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endmodule |