58 lines
2.2 KiB
Verilog
58 lines
2.2 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_arb (
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input wire clk,
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input wire reset,
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// bus select
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input wire select_io_req,
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input wire select_io_rsp,
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// input requets
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VX_csr_req_if csr_core_req_if,
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VX_csr_io_req_if csr_io_req_if,
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// output request
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VX_csr_req_if csr_req_if,
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// input response
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VX_commit_if csr_rsp_if,
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// outputs responses
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VX_commit_if csr_commit_if,
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VX_csr_io_rsp_if csr_io_rsp_if
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);
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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// requests
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assign csr_req_if.valid = (~select_io_req) ? csr_core_req_if.valid : csr_io_req_if.valid;
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assign csr_req_if.wid = (~select_io_req) ? csr_core_req_if.wid : 0;
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assign csr_req_if.tmask = (~select_io_req) ? csr_core_req_if.tmask : 0;
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assign csr_req_if.PC = (~select_io_req) ? csr_core_req_if.PC : 0;
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assign csr_req_if.op_type = (~select_io_req) ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS);
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assign csr_req_if.csr_addr = (~select_io_req) ? csr_core_req_if.csr_addr : csr_io_req_if.addr;
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assign csr_req_if.csr_mask = (~select_io_req) ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
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assign csr_req_if.rd = (~select_io_req) ? csr_core_req_if.rd : 0;
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assign csr_req_if.wb = (~select_io_req) ? csr_core_req_if.wb : 0;
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assign csr_req_if.is_io = select_io_req;
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assign csr_core_req_if.ready = csr_req_if.ready && (~select_io_req);
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assign csr_io_req_if.ready = csr_req_if.ready && select_io_req;
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// responses
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assign csr_io_rsp_if.valid = csr_rsp_if.valid & select_io_rsp;
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assign csr_io_rsp_if.data = csr_rsp_if.data[0];
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assign csr_commit_if.valid = csr_rsp_if.valid & ~select_io_rsp;
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assign csr_commit_if.wid = csr_rsp_if.wid;
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assign csr_commit_if.tmask = csr_rsp_if.tmask;
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assign csr_commit_if.PC = csr_rsp_if.PC;
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assign csr_commit_if.rd = csr_rsp_if.rd;
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assign csr_commit_if.wb = csr_rsp_if.wb;
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assign csr_commit_if.data = csr_rsp_if.data;
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assign csr_rsp_if.ready = select_io_rsp ? csr_io_rsp_if.ready : csr_commit_if.ready;
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endmodule
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