40 lines
1.2 KiB
Verilog
40 lines
1.2 KiB
Verilog
`include "VX_define.vh"
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module VX_gpr_ram (
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input wire clk,
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input wire reset,
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input wire we,
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input wire [4:0] waddr,
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input wire [4:0] raddr1,
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input wire [4:0] raddr2,
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input wire [`NUM_THREADS-1:0] be,
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input wire [`NUM_THREADS-1:0][31:0] wdata,
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output reg [`NUM_THREADS-1:0][31:0] q1,
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output reg [`NUM_THREADS-1:0][31:0] q2
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);
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// Thread Byte Bit
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logic [`NUM_THREADS-1:0][3:0][7:0] ram[31:0];
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always @(posedge clk) begin
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if (reset) begin
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//--
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end else begin
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if (we) begin
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integer t;
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for (t = 0; t < `NUM_THREADS; t = t + 1) begin
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if (be[t]) begin
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ram[waddr][t][0] <= wdata[t][7:0];
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ram[waddr][t][1] <= wdata[t][15:8];
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ram[waddr][t][2] <= wdata[t][23:16];
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ram[waddr][t][3] <= wdata[t][31:24];
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end
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end
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end
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end
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end
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assign q1 = ram[raddr1];
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assign q2 = ram[raddr2];
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endmodule
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