78 lines
2.8 KiB
Systemverilog
78 lines
2.8 KiB
Systemverilog
`ifndef VX_CACHE_CONFIG
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`define VX_CACHE_CONFIG
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`include "VX_define.vh"
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`define REQ_TAG_WIDTH `MAX(CORE_TAG_WIDTH, SNP_REQ_TAG_WIDTH)
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// tag rw byteen tid
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`define REQ_INST_META_WIDTH (`REQ_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS)
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// data metadata word_sel is_snp snp_invalidate
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`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH) + 1 + 1)
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`define BANK_BITS `LOG2UP(NUM_BANKS)
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`define WORD_WIDTH (8 * WORD_SIZE)
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`define BANK_LINE_WIDTH (8 * BANK_LINE_SIZE)
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`define BANK_SIZE (CACHE_SIZE / NUM_BANKS)
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`define BANK_LINE_COUNT (`BANK_SIZE / BANK_LINE_SIZE)
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`define BANK_LINE_WORDS (BANK_LINE_SIZE / WORD_SIZE)
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// Offset select
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`define OFFSET_ADDR_BITS `CLOG2(WORD_SIZE)
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`define OFFSET_ADDR_START 0
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`define OFFSET_ADDR_END (`OFFSET_ADDR_START+`OFFSET_ADDR_BITS-1)
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// Word select
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`define WORD_SELECT_BITS `CLOG2(`BANK_LINE_WORDS)
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`define WORD_SELECT_ADDR_START (1+`OFFSET_ADDR_END)
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`define WORD_SELECT_ADDR_END (`WORD_SELECT_ADDR_START+`WORD_SELECT_BITS-1)
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// Bank select
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`define BANK_SELECT_BITS `CLOG2(NUM_BANKS)
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`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END)
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`define BANK_SELECT_ADDR_END (`BANK_SELECT_ADDR_START+`BANK_SELECT_BITS-1)
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// Line select
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`define LINE_SELECT_BITS `CLOG2(`BANK_LINE_COUNT)
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`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END)
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`define LINE_SELECT_ADDR_END (`LINE_SELECT_ADDR_START+`LINE_SELECT_BITS-1)
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// Tag select
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`define TAG_SELECT_BITS (31-`LINE_SELECT_ADDR_END)
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`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END)
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`define TAG_SELECT_ADDR_END 31
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`define WORD_SELECT_WIDTH `CLOG2(`BANK_LINE_WORDS)
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`define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE))
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`define DRAM_ADDR_WIDTH (32-`CLOG2(BANK_LINE_SIZE))
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`define LINE_ADDR_WIDTH (`DRAM_ADDR_WIDTH-`BANK_SELECT_BITS)
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`define BANK_SELECT_ADDR_RNG (`BANK_SELECT_BITS+`WORD_SELECT_BITS-1):`WORD_SELECT_BITS
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`define LINE_SELECT_ADDR_RNG `WORD_ADDR_WIDTH-1:(`BANK_SELECT_BITS + `WORD_SELECT_BITS)
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`define TAG_LINE_ADDR_RNG `LINE_ADDR_WIDTH-1:`LINE_SELECT_BITS
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`define BASE_ADDR_BITS (`WORD_SELECT_BITS+`OFFSET_ADDR_BITS)
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///////////////////////////////////////////////////////////////////////////////
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`define CORE_REQ_TAG_COUNT ((CORE_TAG_ID_BITS != 0) ? 1 : NUM_REQUESTS)
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`define DRAM_ADDR_BANK(x) x[`BANK_SELECT_BITS-1:0]
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`define DRAM_TO_LINE_ADDR(x) x[`DRAM_ADDR_WIDTH-1:`BANK_SELECT_BITS]
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`define LINE_TO_DRAM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
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`define LINE_TO_BYTE_ADDR(x, i) {x, (32-$bits(x))'(i << (32-$bits(x)-`BANK_SELECT_BITS))}
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`endif
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