c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
151 lines
3.4 KiB
ArmAsm
151 lines
3.4 KiB
ArmAsm
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <VX_config.h>
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#include <VX_types.h>
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#define RISCV_CUSTOM0 0x0B
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.section .init, "ax"
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.global _start
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.type _start, @function
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_start:
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# initialize per-thread registers
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csrr t0, VX_CSR_NUM_WARPS # get num warps
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la t1, init_regs_all
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.insn r RISCV_CUSTOM0, 1, 0, x0, t0, t1 # wspawn t0, t1
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li t0, -1
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.insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0
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jal init_regs
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li t0, 1
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.insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0
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# wait for spawn warps to terminate
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jal vx_wspawn_wait
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# initialize TLS for all warps
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csrr t0, VX_CSR_NUM_WARPS # get num warps
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la t1, init_tls_all
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.insn r RISCV_CUSTOM0, 1, 0, x0, t0, t1 # wspawn t0, t1
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li t0, -1
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.insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0
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call __init_tls
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li t0, 1
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.insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0
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# wait for spawn warps to terminate
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jal vx_wspawn_wait
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# clear BSS segment
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la a0, _edata
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la a2, _end
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sub a2, a2, a0
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li a1, 0
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call memset
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# initialize trap vector
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# la t0, trap_entry
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# csrw mtvec, t0
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# register global termination functions
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la a0, __libc_fini_array
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call atexit
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# run global initialization functions
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call __libc_init_array
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# call main program routine
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call main
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# call exit routine
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tail exit
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.size _start, .-_start
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.section .text
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.type _exit, @function
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.global _exit
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_exit:
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mv s0, a0
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call vx_perf_dump
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mv gp, s0
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.insn r RISCV_CUSTOM0, 0, 0, x0, x0, x0 # tmc x0
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.section .text
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.type init_regs, @function
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.local init_regs
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init_regs:
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# set global pointer register
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.option push
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.option norelax
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la gp, __global_pointer
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.option pop
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# set stack pointer register
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#if (XLEN == 64)
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li t0, (STACK_BASE_ADDR >> 32)
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slli t0, t0, 32
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li sp, (STACK_BASE_ADDR & 0xffffffff)
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or sp, sp, t0
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#else
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li sp, STACK_BASE_ADDR # load stack base address
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#endif
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csrr t0, VX_CSR_MHARTID
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sll t1, t0, STACK_LOG2_SIZE
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sub sp, sp, t1
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# set thread pointer register
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# use address space after BSS region
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# ensure cache line alignment
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la t1, __tcb_aligned_size
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mul t0, t0, t1
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la tp, _end + 63
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add tp, tp, t0
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and tp, tp, -64
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ret
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.section .text
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.type init_regs_all, @function
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.local init_regs_all
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init_regs_all:
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li t0, -1
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.insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0
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jal init_regs
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.insn r RISCV_CUSTOM0, 0, 0, x0, x0, x0 # tmc x0
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ret
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.section .text
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.type init_tls_all, @function
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.local init_tls_all
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init_tls_all:
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li t0, -1
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.insn r RISCV_CUSTOM0, 0, 0, x0, t0, x0 # tmc t0
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call __init_tls
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.insn r RISCV_CUSTOM0, 0, 0, x0, x0, x0 # tmc x0
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ret
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.section .text
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.type vx_wspawn_wait, @function
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.global vx_wspawn_wait
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vx_wspawn_wait:
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csrr t0, VX_CSR_WARP_MASK
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li t1, 1
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bne t0, t1, vx_wspawn_wait
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ret
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.section .data
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.global __dso_handle
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.weak __dso_handle
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__dso_handle:
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.long 0
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