47 lines
1.2 KiB
Verilog
47 lines
1.2 KiB
Verilog
`include "VX_platform.vh"
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module VX_pending_size #(
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parameter SIZE = 1,
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parameter SIZEW = $clog2(SIZE+1)
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) (
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input wire clk,
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input wire reset,
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input wire push,
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input wire pop,
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output wire empty,
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output wire full,
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output wire [SIZEW-1:0] size
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);
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localparam ADDRW = $clog2(SIZE);
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reg [ADDRW-1:0] used_r;
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reg empty_r;
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reg full_r;
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always @(posedge clk) begin
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if (reset) begin
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used_r <= 0;
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empty_r <= 1;
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full_r <= 0;
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end else begin
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assert(!push || !full);
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if (push) begin
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if (!pop) begin
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empty_r <= 0;
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if (used_r == ADDRW'(SIZE-1))
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full_r <= 1;
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end
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end else if (pop) begin
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full_r <= 0;
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if (used_r == ADDRW'(1))
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empty_r <= 1;
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end
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used_r <= used_r + ADDRW'($signed(2'(push && !pop) - 2'(pop && !push)));
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end
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end
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assign empty = empty_r;
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assign full = full_r;
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assign size = {full_r, used_r};
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endmodule |