45 lines
1.1 KiB
Verilog
45 lines
1.1 KiB
Verilog
`include "VX_platform.vh"
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module VX_generic_register #(
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parameter N = 1,
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parameter R = N,
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parameter PASSTHRU = 0
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) (
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input wire clk,
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input wire reset,
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input wire stall,
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input wire flush,
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input wire[N-1:0] data_in,
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output wire[N-1:0] data_out
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);
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if (PASSTHRU) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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`UNUSED_VAR (stall)
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assign data_out = flush ? N'(0) : data_in;
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end else begin
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reg [N-1:0] value;
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if (R != 0) begin
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always @(posedge clk) begin
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if (~stall) begin
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value <= data_in;
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end
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if (reset || flush) begin
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value[N-1:N-R] <= R'(0);
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end
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end
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end else begin
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`UNUSED_VAR (reset)
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`UNUSED_VAR (flush)
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always @(posedge clk) begin
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if (~stall) begin
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value <= data_in;
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end
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end
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end
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assign data_out = value;
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end
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endmodule |