100 lines
3.9 KiB
Verilog
100 lines
3.9 KiB
Verilog
`include "VX_define.vh"
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module VX_mem_arb #(
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parameter NUM_REQUESTS = 1,
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parameter WORD_SIZE = 1,
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parameter TAG_IN_WIDTH = 1,
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parameter TAG_OUT_WIDTH = 1,
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parameter WORD_WIDTH = WORD_SIZE * 8,
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parameter ADDR_WIDTH = 32 - `CLOG2(WORD_SIZE),
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parameter REQS_BITS = `CLOG2(NUM_REQUESTS)
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) (
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input wire clk,
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input wire reset,
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// input requests
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input wire [NUM_REQUESTS-1:0] in_mem_req_valid,
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input wire [NUM_REQUESTS-1:0] in_mem_req_rw,
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input wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] in_mem_req_byteen,
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input wire [NUM_REQUESTS-1:0][ADDR_WIDTH-1:0] in_mem_req_addr,
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input wire [NUM_REQUESTS-1:0][WORD_WIDTH-1:0] in_mem_req_data,
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input wire [NUM_REQUESTS-1:0][TAG_IN_WIDTH-1:0] in_mem_req_tag,
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output wire [NUM_REQUESTS-1:0] in_mem_req_ready,
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// input response
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output wire [NUM_REQUESTS-1:0] in_mem_rsp_valid,
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output wire [NUM_REQUESTS-1:0][WORD_WIDTH-1:0] in_mem_rsp_data,
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output wire [NUM_REQUESTS-1:0][TAG_IN_WIDTH-1:0] in_mem_rsp_tag,
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input wire [NUM_REQUESTS-1:0] in_mem_rsp_ready,
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// output request
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output wire out_mem_req_valid,
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output wire out_mem_req_rw,
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output wire [WORD_SIZE-1:0] out_mem_req_byteen,
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output wire [ADDR_WIDTH-1:0] out_mem_req_addr,
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output wire [WORD_WIDTH-1:0] out_mem_req_data,
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output wire [TAG_OUT_WIDTH-1:0] out_mem_req_tag,
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input wire out_mem_req_ready,
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// output response
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input wire out_mem_rsp_valid,
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input wire [WORD_WIDTH-1:0] out_mem_rsp_data,
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input wire [TAG_OUT_WIDTH-1:0] out_mem_rsp_tag,
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output wire out_mem_rsp_ready
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);
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if (NUM_REQUESTS == 1) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign out_mem_req_valid = in_mem_req_valid;
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assign out_mem_req_rw = in_mem_req_rw;
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assign out_mem_req_byteen = in_mem_req_byteen;
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assign out_mem_req_addr = in_mem_req_addr;
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assign out_mem_req_data = in_mem_req_data;
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assign out_mem_req_tag = in_mem_req_tag;
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assign in_mem_req_ready = out_mem_req_ready;
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assign in_mem_rsp_valid = out_mem_rsp_valid;
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assign in_mem_rsp_data = out_mem_rsp_data;
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assign in_mem_rsp_tag = out_mem_rsp_tag;
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assign out_mem_rsp_ready = in_mem_rsp_ready;
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end else begin
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reg [REQS_BITS-1:0] bus_req_sel;
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always @(posedge clk) begin
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if (reset) begin
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bus_req_sel <= 0;
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end else begin
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bus_req_sel <= bus_req_sel + 1;
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end
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end
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assign out_mem_req_valid = in_mem_req_valid [bus_req_sel];
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assign out_mem_req_rw = in_mem_req_rw [bus_req_sel];
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assign out_mem_req_byteen = in_mem_req_byteen [bus_req_sel];
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assign out_mem_req_addr = in_mem_req_addr [bus_req_sel];
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assign out_mem_req_data = in_mem_req_data [bus_req_sel];
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assign out_mem_req_tag = {in_mem_req_tag [bus_req_sel], REQS_BITS'(bus_req_sel)};
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genvar i;
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign in_mem_req_ready[i] = out_mem_req_ready && (bus_req_sel == REQS_BITS'(i));
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end
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wire [REQS_BITS-1:0] bus_rsp_sel = out_mem_rsp_tag[REQS_BITS-1:0];
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign in_mem_rsp_valid[i] = out_mem_rsp_valid && (bus_rsp_sel == REQS_BITS'(i));
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assign in_mem_rsp_data[i] = out_mem_rsp_data;
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assign in_mem_rsp_tag[i] = out_mem_rsp_tag[REQS_BITS +: TAG_IN_WIDTH];
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end
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assign out_mem_rsp_ready = out_mem_rsp_valid ? in_mem_rsp_ready[bus_rsp_sel] : 0;
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end
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endmodule |