16 lines
395 B
Systemverilog
16 lines
395 B
Systemverilog
`include "VX_tex_define.vh"
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module VX_tex_lerp (
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input wire [3:0][7:0] in1,
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input wire [3:0][7:0] in2,
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input wire [8:0] alpha,
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input wire [7:0] beta,
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output wire [3:0][7:0] out
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);
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for (genvar i = 0; i < 4; ++i) begin
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wire [16:0] sum = in1[i] * alpha + in2[i] * beta;
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`UNUSED_VAR (sum)
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assign out[i] = sum[15:8];
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end
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endmodule |