83 lines
3.0 KiB
Verilog
83 lines
3.0 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_dram_arb #(
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parameter BANK_LINE_SIZE = 1,
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parameter NUM_REQUESTS = 1,
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parameter CORE_TAG_WIDTH = 1,
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parameter DRAM_TAG_WIDTH = 1
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) (
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input wire clk,
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input wire reset,
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// Core request
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input wire [NUM_REQUESTS-1:0] core_req_read,
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input wire [NUM_REQUESTS-1:0] core_req_write,
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input wire [NUM_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] core_req_addr,
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input wire [NUM_REQUESTS-1:0][`BANK_LINE_WIDTH-1:0] core_req_data,
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input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
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output reg [NUM_REQUESTS-1:0] core_req_ready,
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// Core response
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output wire [NUM_REQUESTS-1:0] core_rsp_valid,
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output wire [NUM_REQUESTS-1:0][`BANK_LINE_WIDTH-1:0]core_rsp_data,
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output wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
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input wire [NUM_REQUESTS-1:0] core_rsp_ready,
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// DRAM request
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output reg dram_req_read,
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output reg dram_req_write,
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output reg [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output reg [`BANK_LINE_WIDTH-1:0] dram_req_data,
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output reg [DRAM_TAG_WIDTH-1:0] dram_req_tag,
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input wire dram_req_ready,
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// DRAM response
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input wire dram_rsp_valid,
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input wire [`BANK_LINE_WIDTH-1:0] dram_rsp_data,
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input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
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output wire dram_rsp_ready
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);
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reg [`REQS_BITS-1:0] bus_req_idx;
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always @(posedge clk) begin
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if (reset) begin
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bus_req_idx <= 0;
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end else begin
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bus_req_idx <= bus_req_idx + 1;
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end
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end
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integer i;
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generate
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always @(*) begin
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dram_req_read = 0;
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dram_req_write = 0;
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dram_req_addr = 'z;
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dram_req_data = 'z;
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dram_req_tag = 'z;
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for (i = 0; i < NUM_REQUESTS; i++) begin
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if (bus_req_idx == (`REQS_BITS)'(i)) begin
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dram_req_read = core_req_read[i];
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dram_req_write = core_req_write[i];
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dram_req_addr = core_req_addr[i];
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dram_req_data = core_req_data[i];
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dram_req_tag = {core_req_tag[i], (`REQS_BITS)'(i)};
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core_req_ready[i] = dram_req_ready;
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end else begin
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core_req_ready[i] = 0;
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end
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end
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end
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endgenerate
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genvar j;
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wire [`REQS_BITS-1:0] bus_rsp_idx = dram_rsp_tag[`REQS_BITS-1:0];
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for (j = 0; j < NUM_REQUESTS; j++) begin
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assign core_rsp_valid[j] = dram_rsp_valid && (bus_rsp_idx == (`REQS_BITS)'(j));
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assign core_rsp_data[j] = dram_rsp_data;
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assign core_rsp_tag[j] = dram_rsp_tag[`REQS_BITS +: CORE_TAG_WIDTH];
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end
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assign dram_rsp_ready = core_rsp_ready[bus_rsp_idx];
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endmodule |