Blaise Tine cd29362d10 fixed FPU handshake, optimized writeback's critical path

2020-08-07 10:11:54 -07:00

..

VX_cam_buffer.v

pipeline optimization

2020-07-30 03:06:01 -07:00

VX_countones.v

modelsim fixes && pipeline optimization

2020-07-28 14:20:23 -07:00

VX_divide.v

added altera fpu modules

2020-08-05 15:53:59 -07:00

VX_fair_arbiter.v

modelsim fixes && pipeline optimization

2020-07-28 14:20:23 -07:00

VX_fixed_arbiter.v

modelsim fixes && pipeline optimization

2020-07-28 14:20:23 -07:00

VX_generic_queue.v

merged fpu_port branch

2020-07-31 17:13:22 -04:00

VX_generic_register.v

modelsim fixes && pipeline optimization

2020-07-28 14:20:23 -07:00

VX_index_queue.v

fixed FPU handshake, optimized writeback's critical path

2020-08-07 10:11:54 -07:00

VX_matrix_arbiter.v

modelsim fixes && pipeline optimization

2020-07-28 14:20:23 -07:00

VX_multiplier.v

added altera fpu modules

2020-08-05 15:53:59 -07:00

VX_onehot_encooder.v

modelsim fixes && pipeline optimization

2020-07-28 14:20:23 -07:00

VX_priority_encoder.v

modelsim fixes && pipeline optimization

2020-07-28 14:20:23 -07:00

VX_rr_arbiter.v

modelsim fixes && pipeline optimization

2020-07-28 14:20:23 -07:00

VX_scope.v

modelsim fixes && pipeline optimization

2020-07-28 14:20:23 -07:00

VX_shift_register.v

added altera fpu modules

2020-08-05 15:53:59 -07:00