29 lines
728 B
Verilog
29 lines
728 B
Verilog
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`include "../VX_cache/VX_cache_config.v"
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`ifndef VX_GPU_DRAM_DCACHE_REQ
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`define VX_GPU_DRAM_DCACHE_REQ
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interface VX_gpu_dcache_dram_req_inter ();
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// DRAM Request
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wire dram_req;
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wire dram_req_write;
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wire dram_req_read;
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wire [31:0] dram_req_addr;
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wire [31:0] dram_req_size;
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wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data;
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// Snoop
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wire dram_because_of_snp;
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wire dram_snp_full;
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// DRAM Cache can't accept response
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wire dram_fill_accept;
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endinterface
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`endif |