d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
68 lines
1.8 KiB
Systemverilog
68 lines
1.8 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_index_buffer #(
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter LUTRAM = 1,
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parameter ADDRW = `LOG2UP(SIZE)
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) (
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input wire clk,
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input wire reset,
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output wire [ADDRW-1:0] write_addr,
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input wire [DATAW-1:0] write_data,
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input wire acquire_en,
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input wire [ADDRW-1:0] read_addr,
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output wire [DATAW-1:0] read_data,
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input wire release_en,
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output wire empty,
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output wire full
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);
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VX_allocator #(
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.SIZE (SIZE)
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) allocator (
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.clk (clk),
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.reset (reset),
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.acquire_en (acquire_en),
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.acquire_addr (write_addr),
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.release_en (release_en),
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.release_addr (read_addr),
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.empty (empty),
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.full (full)
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);
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VX_dp_ram #(
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.DATAW (DATAW),
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.SIZE (SIZE),
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.LUTRAM (LUTRAM)
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) data_table (
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.clk (clk),
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.read (1'b1),
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.write (acquire_en),
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`UNUSED_PIN (wren),
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.waddr (write_addr),
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.wdata (write_data),
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.raddr (read_addr),
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.rdata (read_data)
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);
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endmodule
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`TRACING_ON
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