c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
550 lines
21 KiB
Systemverilog
550 lines
21 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_cache_define.vh"
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module VX_cache_bank #(
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parameter `STRING INSTANCE_ID= "",
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parameter BANK_ID = 0,
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// Number of Word requests per cycle
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parameter NUM_REQS = 1,
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// Size of cache in bytes
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parameter CACHE_SIZE = 1024,
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// Size of line inside a bank in bytes
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parameter LINE_SIZE = 16,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Number of associative ways
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parameter NUM_WAYS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 4,
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// Core Response Queue Size
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parameter CRSQ_SIZE = 1,
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// Miss Reserv Queue Knob
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parameter MSHR_SIZE = 1,
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// Memory Request Queue Size
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parameter MREQ_SIZE = 1,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Request debug identifier
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parameter UUID_WIDTH = 0,
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// core request tag size
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parameter TAG_WIDTH = UUID_WIDTH + 1,
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// Core response output register
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parameter CORE_OUT_REG = 0,
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// Memory request output register
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parameter MEM_OUT_REG = 0,
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parameter MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE),
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parameter REQ_SEL_WIDTH = `UP(`CS_REQ_SEL_BITS),
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parameter WORD_SEL_WIDTH = `UP(`CS_WORD_SEL_BITS)
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) (
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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output wire perf_read_misses,
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output wire perf_write_misses,
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output wire perf_mshr_stalls,
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`endif
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// Core Request
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input wire core_req_valid,
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input wire [`CS_LINE_ADDR_WIDTH-1:0] core_req_addr,
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input wire core_req_rw,
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input wire [WORD_SEL_WIDTH-1:0] core_req_wsel,
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input wire [WORD_SIZE-1:0] core_req_byteen,
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input wire [`CS_WORD_WIDTH-1:0] core_req_data,
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input wire [TAG_WIDTH-1:0] core_req_tag,
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input wire [REQ_SEL_WIDTH-1:0] core_req_idx,
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output wire core_req_ready,
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// Core Response
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output wire core_rsp_valid,
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output wire [`CS_WORD_WIDTH-1:0] core_rsp_data,
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output wire [TAG_WIDTH-1:0] core_rsp_tag,
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output wire [REQ_SEL_WIDTH-1:0] core_rsp_idx,
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input wire core_rsp_ready,
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// Memory request
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output wire mem_req_valid,
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output wire [`CS_LINE_ADDR_WIDTH-1:0] mem_req_addr,
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output wire mem_req_rw,
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output wire [WORD_SEL_WIDTH-1:0] mem_req_wsel,
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output wire [WORD_SIZE-1:0] mem_req_byteen,
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output wire [`CS_WORD_WIDTH-1:0] mem_req_data,
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output wire [MSHR_ADDR_WIDTH-1:0] mem_req_id,
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input wire mem_req_ready,
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// Memory response
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input wire mem_rsp_valid,
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input wire [`CS_LINE_WIDTH-1:0] mem_rsp_data,
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input wire [MSHR_ADDR_WIDTH-1:0] mem_rsp_id,
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output wire mem_rsp_ready,
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// initialization
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input wire init_enable,
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input wire [`CS_LINE_SEL_BITS-1:0] init_line_sel
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);
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`IGNORE_UNUSED_BEGIN
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wire [`UP(UUID_WIDTH)-1:0] req_uuid_sel, req_uuid_st0, req_uuid_st1;
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`IGNORE_UNUSED_END
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wire crsq_stall;
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wire mshr_alm_full;
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wire mreq_alm_full;
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wire [`CS_LINE_ADDR_WIDTH-1:0] mem_rsp_addr;
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wire replay_valid;
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wire [`CS_LINE_ADDR_WIDTH-1:0] replay_addr;
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wire replay_rw;
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wire [WORD_SEL_WIDTH-1:0] replay_wsel;
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wire [WORD_SIZE-1:0] replay_byteen;
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wire [`CS_WORD_WIDTH-1:0] replay_data;
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wire [TAG_WIDTH-1:0] replay_tag;
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wire [REQ_SEL_WIDTH-1:0] replay_idx;
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wire [MSHR_ADDR_WIDTH-1:0] replay_id;
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wire replay_ready;
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wire [`CS_LINE_ADDR_WIDTH-1:0] addr_sel, addr_st0, addr_st1;
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wire rw_st0, rw_st1;
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wire [WORD_SEL_WIDTH-1:0] wsel_st0, wsel_st1;
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wire [WORD_SIZE-1:0] byteen_st0, byteen_st1;
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wire [REQ_SEL_WIDTH-1:0] req_idx_st0, req_idx_st1;
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wire [TAG_WIDTH-1:0] tag_st0, tag_st1;
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wire [`CS_WORD_WIDTH-1:0] read_data_st1;
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wire [`CS_LINE_WIDTH-1:0] data_sel, data_st0, data_st1;
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wire [MSHR_ADDR_WIDTH-1:0] replay_id_st0, mshr_id_st0, mshr_id_st1;
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wire valid_sel, valid_st0, valid_st1;
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wire is_init_st0;
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wire is_creq_st0, is_creq_st1;
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wire is_fill_st0, is_fill_st1;
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wire is_replay_st0, is_replay_st1;
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wire [MSHR_ADDR_WIDTH-1:0] mshr_alloc_id_st0;
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wire [MSHR_ADDR_WIDTH-1:0] mshr_tail_st0, mshr_tail_st1;
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wire mshr_pending_st0, mshr_pending_st1;
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wire rdw_hazard_st0;
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reg rdw_hazard_st1;
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wire pipe_stall = crsq_stall || rdw_hazard_st1;
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// inputs arbitration:
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// mshr replay has highest priority to maximize utilization since there is no miss.
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// handle memory responses next to prevent deadlock with potential memory request from a miss.
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wire replay_grant = ~init_enable;
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wire replay_enable = replay_grant && replay_valid;
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wire fill_grant = ~init_enable && ~replay_enable;
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wire fill_enable = fill_grant && mem_rsp_valid;
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wire creq_grant = ~init_enable && ~replay_enable && ~fill_enable;
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wire creq_enable = creq_grant && core_req_valid;
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assign replay_ready = replay_grant
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&& ~rdw_hazard_st0
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&& ~pipe_stall;
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assign mem_rsp_ready = fill_grant
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&& ~pipe_stall;
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assign core_req_ready = creq_grant
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&& ~mreq_alm_full
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&& ~mshr_alm_full
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&& ~pipe_stall;
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wire init_fire = init_enable;
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wire replay_fire = replay_valid && replay_ready;
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wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready;
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wire core_req_fire = core_req_valid && core_req_ready;
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wire [TAG_WIDTH-1:0] mshr_creq_tag = replay_enable ? replay_tag : core_req_tag;
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if (UUID_WIDTH != 0) begin
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assign req_uuid_sel = mshr_creq_tag[TAG_WIDTH-1 -: UUID_WIDTH];
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end else begin
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assign req_uuid_sel = 0;
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end
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`UNUSED_VAR (mshr_creq_tag)
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assign valid_sel = init_fire || replay_fire || mem_rsp_fire || core_req_fire;
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assign addr_sel = init_enable ? `CS_LINE_ADDR_WIDTH'(init_line_sel) :
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(replay_valid ? replay_addr :
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(mem_rsp_valid ? mem_rsp_addr : core_req_addr));
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assign data_sel[`CS_WORD_WIDTH-1:0] = (mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data[`CS_WORD_WIDTH-1:0] : (replay_valid ? replay_data : core_req_data);
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for (genvar i = `CS_WORD_WIDTH; i < `CS_LINE_WIDTH; ++i) begin
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assign data_sel[i] = mem_rsp_data[i];
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end
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VX_pipe_register #(
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.DATAW (1 + 1 + 1 + 1 + 1 + `CS_LINE_ADDR_WIDTH + `CS_LINE_WIDTH + 1 + WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + TAG_WIDTH + MSHR_ADDR_WIDTH),
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.RESETW (1)
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) pipe_reg0 (
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.clk (clk),
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.reset (reset),
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.enable (~pipe_stall),
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.data_in ({
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valid_sel,
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init_enable,
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replay_enable,
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fill_enable,
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creq_enable,
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addr_sel,
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data_sel,
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replay_valid ? replay_rw : core_req_rw,
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replay_valid ? replay_byteen : core_req_byteen,
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replay_valid ? replay_wsel : core_req_wsel,
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replay_valid ? replay_idx : core_req_idx,
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replay_valid ? replay_tag : core_req_tag,
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replay_id
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}),
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.data_out ({valid_st0, is_init_st0, is_replay_st0, is_fill_st0, is_creq_st0, addr_st0, data_st0, rw_st0, byteen_st0, wsel_st0, req_idx_st0, tag_st0, replay_id_st0})
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);
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if (UUID_WIDTH != 0) begin
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assign req_uuid_st0 = tag_st0[TAG_WIDTH-1 -: UUID_WIDTH];
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end else begin
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assign req_uuid_st0 = 0;
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end
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wire do_creq_rd_st0 = valid_st0 && is_creq_st0 && ~rw_st0;
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wire do_fill_st0 = valid_st0 && is_fill_st0;
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wire do_init_st0 = valid_st0 && is_init_st0;
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wire do_lookup_st0 = valid_st0 && ~(is_fill_st0 || is_init_st0);
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wire [`CS_WORD_WIDTH-1:0] write_data_st0 = data_st0[`CS_WORD_WIDTH-1:0];
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wire [NUM_WAYS-1:0] tag_matches_st0, tag_matches_st1;
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wire [NUM_WAYS-1:0] way_sel_st0, way_sel_st1;
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`RESET_RELAY (tag_reset, reset);
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VX_cache_tags #(
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.INSTANCE_ID(INSTANCE_ID),
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.BANK_ID (BANK_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.LINE_SIZE (LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.NUM_WAYS (NUM_WAYS),
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.WORD_SIZE (WORD_SIZE),
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.UUID_WIDTH (UUID_WIDTH)
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) cache_tags (
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.clk (clk),
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.reset (tag_reset),
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.req_uuid (req_uuid_st0),
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.stall (pipe_stall),
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// read/Fill
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.lookup (do_lookup_st0),
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.line_addr (addr_st0),
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.fill (do_fill_st0),
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.init (do_init_st0),
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.way_sel (way_sel_st0),
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.tag_matches(tag_matches_st0)
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);
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assign mshr_id_st0 = is_creq_st0 ? mshr_alloc_id_st0 : replay_id_st0;
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VX_pipe_register #(
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.DATAW (1 + 1 + 1 + 1 + 1 + `CS_LINE_ADDR_WIDTH + `CS_LINE_WIDTH + WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + TAG_WIDTH + MSHR_ADDR_WIDTH + MSHR_ADDR_WIDTH + NUM_WAYS + NUM_WAYS + 1),
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.RESETW (1)
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) pipe_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (~pipe_stall),
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.data_in ({valid_st0, is_replay_st0, is_fill_st0, is_creq_st0, rw_st0, addr_st0, data_st0, byteen_st0, wsel_st0, req_idx_st0, tag_st0, mshr_id_st0, mshr_tail_st0, tag_matches_st0, way_sel_st0, mshr_pending_st0}),
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.data_out ({valid_st1, is_replay_st1, is_fill_st1, is_creq_st1, rw_st1, addr_st1, data_st1, byteen_st1, wsel_st1, req_idx_st1, tag_st1, mshr_id_st1, mshr_tail_st1, tag_matches_st1, way_sel_st1, mshr_pending_st1})
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);
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// we have a tag hit
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wire is_hit_st1 = (| tag_matches_st1);
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if (UUID_WIDTH != 0) begin
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assign req_uuid_st1 = tag_st1[TAG_WIDTH-1 -: UUID_WIDTH];
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end else begin
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assign req_uuid_st1 = 0;
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end
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wire do_creq_rd_st1 = valid_st1 && is_creq_st1 && ~rw_st1;
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wire do_creq_wr_st1 = valid_st1 && is_creq_st1 && rw_st1;
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wire do_fill_st1 = valid_st1 && is_fill_st1;
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wire do_replay_rd_st1 = valid_st1 && is_replay_st1 && ~rw_st1;
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wire do_replay_wr_st1 = valid_st1 && is_replay_st1 && rw_st1;
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wire do_read_hit_st1 = do_creq_rd_st1 && is_hit_st1;
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wire do_read_miss_st1 = do_creq_rd_st1 && ~is_hit_st1;
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wire do_write_hit_st1 = do_creq_wr_st1 && is_hit_st1;
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wire do_write_miss_st1= do_creq_wr_st1 && ~is_hit_st1;
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`UNUSED_VAR (do_write_miss_st1)
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// ensure mshr replay always get a hit
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`RUNTIME_ASSERT (~(valid_st1 && is_replay_st1) || is_hit_st1, ("runtime error: invalid mshr replay"));
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// detect BRAM's read-during-write hazard
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assign rdw_hazard_st0 = do_fill_st0; // after a fill
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always @(posedge clk) begin
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rdw_hazard_st1 <= (do_creq_rd_st0 && do_write_hit_st1 && (addr_st0 == addr_st1))
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&& ~rdw_hazard_st1; // after a write to same address
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end
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wire [`CS_WORD_WIDTH-1:0] write_data_st1 = data_st1[`CS_WORD_WIDTH-1:0];
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wire [`CS_LINE_WIDTH-1:0] fill_data_st1 = data_st1;
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`RESET_RELAY (data_reset, reset);
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VX_cache_data #(
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.INSTANCE_ID (INSTANCE_ID),
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.BANK_ID (BANK_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.LINE_SIZE (LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.NUM_WAYS (NUM_WAYS),
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.WORD_SIZE (WORD_SIZE),
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.WRITE_ENABLE (WRITE_ENABLE),
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.UUID_WIDTH (UUID_WIDTH)
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) cache_data (
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.clk (clk),
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.reset (data_reset),
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.req_uuid (req_uuid_st1),
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.stall (pipe_stall),
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.read (do_read_hit_st1 || do_replay_rd_st1),
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.fill (do_fill_st1),
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.write (do_write_hit_st1 || do_replay_wr_st1),
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.way_sel (way_sel_st1 | tag_matches_st1),
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.line_addr (addr_st1),
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.wsel (wsel_st1),
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.byteen (byteen_st1),
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.fill_data (fill_data_st1),
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.write_data (write_data_st1),
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.read_data (read_data_st1)
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);
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wire [MSHR_SIZE-1:0] mshr_matches_st0;
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wire mshr_allocate_st0 = valid_st0 && is_creq_st0 && ~pipe_stall;
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wire mshr_lookup_st0 = mshr_allocate_st0;
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wire mshr_finalize_st1 = valid_st1 && is_creq_st1 && ~pipe_stall;
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wire mshr_release_st1 = is_hit_st1 || (rw_st1 && ~mshr_pending_st1);
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VX_pending_size #(
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.SIZE (MSHR_SIZE)
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) mshr_pending_size (
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.clk (clk),
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.reset (reset),
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.incr (core_req_fire),
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.decr (replay_fire || (mshr_finalize_st1 && mshr_release_st1)),
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.full (mshr_alm_full),
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`UNUSED_PIN (size),
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`UNUSED_PIN (empty)
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);
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`RESET_RELAY (mshr_reset, reset);
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VX_cache_mshr #(
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.INSTANCE_ID (INSTANCE_ID),
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.BANK_ID (BANK_ID),
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.LINE_SIZE (LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.MSHR_SIZE (MSHR_SIZE),
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.UUID_WIDTH (UUID_WIDTH),
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.DATA_WIDTH (WORD_SEL_WIDTH + WORD_SIZE + `CS_WORD_WIDTH + TAG_WIDTH + REQ_SEL_WIDTH)
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) cache_mshr (
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.clk (clk),
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.reset (mshr_reset),
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.deq_req_uuid (req_uuid_sel),
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.lkp_req_uuid (req_uuid_st0),
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.fin_req_uuid (req_uuid_st1),
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// memory fill
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.fill_valid (mem_rsp_fire),
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.fill_id (mem_rsp_id),
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.fill_addr (mem_rsp_addr),
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// dequeue
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.dequeue_valid (replay_valid),
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.dequeue_addr (replay_addr),
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.dequeue_rw (replay_rw),
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.dequeue_data ({replay_wsel, replay_byteen, replay_data, replay_tag, replay_idx}),
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.dequeue_id (replay_id),
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.dequeue_ready (replay_ready),
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// allocate
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.allocate_valid (mshr_allocate_st0),
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.allocate_addr (addr_st0),
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.allocate_rw (rw_st0),
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.allocate_data ({wsel_st0, byteen_st0, write_data_st0, tag_st0, req_idx_st0}),
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.allocate_id (mshr_alloc_id_st0),
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.allocate_tail (mshr_tail_st0),
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`UNUSED_PIN (allocate_ready),
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// lookup
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.lookup_valid (mshr_lookup_st0),
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.lookup_addr (addr_st0),
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.lookup_matches (mshr_matches_st0),
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// finalize
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.finalize_valid (mshr_finalize_st1),
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.finalize_release(mshr_release_st1),
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.finalize_pending(mshr_pending_st1),
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.finalize_id (mshr_id_st1),
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.finalize_tail (mshr_tail_st1)
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);
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// ignore allocated id from mshr matches
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wire [MSHR_SIZE-1:0] lookup_matches;
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for (genvar i = 0; i < MSHR_SIZE; ++i) begin
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assign lookup_matches[i] = (i != mshr_alloc_id_st0) && mshr_matches_st0[i];
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end
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assign mshr_pending_st0 = (| lookup_matches);
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// schedule core response
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wire crsq_valid, crsq_ready;
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wire [`CS_WORD_WIDTH-1:0] crsq_data;
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wire [REQ_SEL_WIDTH-1:0] crsq_idx;
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wire [TAG_WIDTH-1:0] crsq_tag;
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|
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assign crsq_valid = do_read_hit_st1 || do_replay_rd_st1;
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assign crsq_idx = req_idx_st1;
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assign crsq_data = read_data_st1;
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assign crsq_tag = tag_st1;
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|
|
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`RESET_RELAY (crsp_reset, reset);
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|
|
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VX_elastic_buffer #(
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.DATAW (TAG_WIDTH + `CS_WORD_WIDTH + REQ_SEL_WIDTH),
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.SIZE (CRSQ_SIZE),
|
|
.OUT_REG (CORE_OUT_REG)
|
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) core_rsp_queue (
|
|
.clk (clk),
|
|
.reset (crsp_reset),
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.valid_in (crsq_valid && ~rdw_hazard_st1),
|
|
.ready_in (crsq_ready),
|
|
.data_in ({crsq_tag, crsq_data, crsq_idx}),
|
|
.data_out ({core_rsp_tag, core_rsp_data, core_rsp_idx}),
|
|
.valid_out (core_rsp_valid),
|
|
.ready_out (core_rsp_ready)
|
|
);
|
|
|
|
assign crsq_stall = crsq_valid && ~crsq_ready;
|
|
|
|
// schedule memory request
|
|
|
|
wire mreq_push, mreq_pop, mreq_empty;
|
|
wire [`CS_WORD_WIDTH-1:0] mreq_data;
|
|
wire [WORD_SIZE-1:0] mreq_byteen;
|
|
wire [WORD_SEL_WIDTH-1:0] mreq_wsel;
|
|
wire [`CS_LINE_ADDR_WIDTH-1:0] mreq_addr;
|
|
wire [MSHR_ADDR_WIDTH-1:0] mreq_id;
|
|
wire mreq_rw;
|
|
|
|
assign mreq_push = (do_read_miss_st1 && ~mshr_pending_st1)
|
|
|| do_creq_wr_st1;
|
|
|
|
assign mreq_pop = mem_req_valid && mem_req_ready;
|
|
|
|
assign mreq_rw = WRITE_ENABLE && rw_st1;
|
|
assign mreq_addr = addr_st1;
|
|
assign mreq_id = mshr_id_st1;
|
|
assign mreq_wsel = wsel_st1;
|
|
assign mreq_byteen = byteen_st1;
|
|
assign mreq_data = write_data_st1;
|
|
|
|
`RESET_RELAY (mreq_reset, reset);
|
|
|
|
VX_fifo_queue #(
|
|
.DATAW (1 + `CS_LINE_ADDR_WIDTH + MSHR_ADDR_WIDTH + WORD_SIZE + WORD_SEL_WIDTH + `CS_WORD_WIDTH),
|
|
.DEPTH (MREQ_SIZE),
|
|
.ALM_FULL (MREQ_SIZE-2),
|
|
.OUT_REG (MEM_OUT_REG)
|
|
) mem_req_queue (
|
|
.clk (clk),
|
|
.reset (mreq_reset),
|
|
.push (mreq_push),
|
|
.pop (mreq_pop),
|
|
.data_in ({mreq_rw, mreq_addr, mreq_id, mreq_byteen, mreq_wsel, mreq_data}),
|
|
.data_out ({mem_req_rw, mem_req_addr, mem_req_id, mem_req_byteen, mem_req_wsel, mem_req_data}),
|
|
.empty (mreq_empty),
|
|
.alm_full (mreq_alm_full),
|
|
`UNUSED_PIN (full),
|
|
`UNUSED_PIN (alm_empty),
|
|
`UNUSED_PIN (size)
|
|
);
|
|
|
|
assign mem_req_valid = ~mreq_empty;
|
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
|
|
`ifdef PERF_ENABLE
|
|
assign perf_read_misses = do_read_miss_st1;
|
|
assign perf_write_misses = do_write_miss_st1;
|
|
assign perf_mshr_stalls = mshr_alm_full;
|
|
`endif
|
|
|
|
`ifdef DBG_TRACE_CACHE_BANK
|
|
wire crsq_fire = crsq_valid && crsq_ready;
|
|
wire pipeline_stall = (replay_valid || mem_rsp_valid || core_req_valid)
|
|
&& ~(replay_fire || mem_rsp_fire || core_req_fire);
|
|
always @(posedge clk) begin
|
|
if (pipeline_stall) begin
|
|
`TRACE(3, ("%d: *** %s-bank%0d stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INSTANCE_ID, BANK_ID, crsq_stall, mreq_alm_full, mshr_alm_full));
|
|
end
|
|
if (init_enable) begin
|
|
`TRACE(2, ("%d: %s-bank%0d init: addr=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(init_line_sel, BANK_ID)));
|
|
end
|
|
if (mem_rsp_fire) begin
|
|
`TRACE(2, ("%d: %s-bank%0d fill-rsp: addr=0x%0h, mshr_id=%0d, data=0x%0h\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mem_rsp_addr, BANK_ID), mem_rsp_id, mem_rsp_data));
|
|
end
|
|
if (replay_fire) begin
|
|
`TRACE(2, ("%d: %s-bank%0d mshr-pop: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(replay_addr, BANK_ID), replay_tag, replay_idx, req_uuid_sel));
|
|
end
|
|
if (core_req_fire) begin
|
|
if (core_req_rw)
|
|
`TRACE(2, ("%d: %s-bank%0d core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, core_req_byteen, core_req_data, req_uuid_sel));
|
|
else
|
|
`TRACE(2, ("%d: %s-bank%0d core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(core_req_addr, BANK_ID), core_req_tag, core_req_idx, req_uuid_sel));
|
|
end
|
|
if (crsq_fire) begin
|
|
`TRACE(2, ("%d: %s-bank%0d core-rd-rsp: addr=0x%0h, tag=0x%0h, req_idx=%0d, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_idx, crsq_data, req_uuid_st1));
|
|
end
|
|
if (mreq_push) begin
|
|
if (do_creq_wr_st1)
|
|
`TRACE(2, ("%d: %s-bank%0d writethrough: addr=0x%0h, byteen=%b, data=0x%0h (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_byteen, mreq_data, req_uuid_st1));
|
|
else
|
|
`TRACE(2, ("%d: %s-bank%0d fill-req: addr=0x%0h, mshr_id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID, `CS_LINE_TO_FULL_ADDR(mreq_addr, BANK_ID), mreq_id, req_uuid_st1));
|
|
end
|
|
end
|
|
`endif
|
|
|
|
endmodule
|