167 lines
5.8 KiB
Verilog
167 lines
5.8 KiB
Verilog
`include "VX_define.vh"
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module VX_generic_queue #(
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parameter DATAW = 1,
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parameter SIZE = 16,
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parameter BUFFERED_OUTPUT = 1
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) (
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input wire clk,
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input wire reset,
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input wire push,
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input wire pop,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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output wire empty,
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output wire full,
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output wire [`LOG2UP(SIZE+1)-1:0] size
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);
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`STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!")
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reg [`LOG2UP(SIZE+1)-1:0] size_r;
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wire reading;
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wire writing;
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assign reading = pop && !empty;
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assign writing = push && !full;
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if (SIZE == 1) begin // (SIZE == 1)
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reg [DATAW-1:0] head_r;
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always @(posedge clk) begin
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if (reset) begin
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head_r <= 0;
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size_r <= 0;
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end else begin
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if (writing && !reading) begin
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size_r <= 1;
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end else if (reading && !writing) begin
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size_r <= 0;
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end
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if (writing) begin
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head_r <= data_in;
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end
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end
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end
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assign data_out = head_r;
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assign empty = (size_r == 0);
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assign full = (size_r != 0);
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assign size = size_r;
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end else begin // (SIZE > 1)
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`ifdef QUEUE_FORCE_MLAB
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(* syn_ramstyle = "mlab" *) reg [DATAW-1:0] data [SIZE-1:0];
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`else
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reg [DATAW-1:0] data [SIZE-1:0];
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`endif
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if (0 == BUFFERED_OUTPUT) begin
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reg [`LOG2UP(SIZE):0] rd_ptr_r;
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reg [`LOG2UP(SIZE):0] wr_ptr_r;
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wire [`LOG2UP(SIZE)-1:0] rd_ptr_a = rd_ptr_r[`LOG2UP(SIZE)-1:0];
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wire [`LOG2UP(SIZE)-1:0] wr_ptr_a = wr_ptr_r[`LOG2UP(SIZE)-1:0];
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always @(posedge clk) begin
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if (reset) begin
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rd_ptr_r <= 0;
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wr_ptr_r <= 0;
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size_r <= 0;
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end else begin
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if (writing) begin
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data[wr_ptr_a] <= data_in;
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wr_ptr_r <= wr_ptr_r + 1;
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if (!reading) begin
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size_r <= size_r + 1;
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end
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end
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if (reading) begin
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rd_ptr_r <= rd_ptr_r + 1;
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if (!writing) begin
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size_r <= size_r - 1;
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end
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end
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end
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end
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assign data_out = data[rd_ptr_a];
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assign empty = (wr_ptr_r == rd_ptr_r);
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assign full = (wr_ptr_a == rd_ptr_a) && (wr_ptr_r[`LOG2UP(SIZE)] != rd_ptr_r[`LOG2UP(SIZE)]);
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assign size = size_r;
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end else begin
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reg [DATAW-1:0] head_r;
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reg [DATAW-1:0] curr_r;
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reg [`LOG2UP(SIZE)-1:0] wr_ptr_r;
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reg [`LOG2UP(SIZE)-1:0] rd_ptr_r;
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reg [`LOG2UP(SIZE)-1:0] rd_ptr_next_r;
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reg empty_r;
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reg full_r;
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reg bypass_r;
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always @(posedge clk) begin
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if (reset) begin
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size_r <= 0;
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head_r <= 0;
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curr_r <= 0;
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wr_ptr_r <= 0;
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rd_ptr_r <= 0;
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rd_ptr_next_r <= 1;
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empty_r <= 1;
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full_r <= 0;
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end else begin
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if (writing) begin
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data[wr_ptr_r] <= data_in;
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wr_ptr_r <= wr_ptr_r + 1;
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if (!reading) begin
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empty_r <= 0;
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if (size_r == ($bits(size_r)'(SIZE-1))) begin
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full_r <= 1;
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end
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size_r <= size_r + 1;
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end
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end
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if (reading) begin
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rd_ptr_r <= rd_ptr_next_r;
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if (SIZE > 2) begin
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rd_ptr_next_r <= rd_ptr_r + $bits(rd_ptr_r)'(2);
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end else begin // (SIZE == 2);
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rd_ptr_next_r <= ~rd_ptr_next_r;
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end
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if (!writing) begin
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if (size_r == 1) begin
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assert(rd_ptr_next_r == wr_ptr_r);
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empty_r <= 1;
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end;
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full_r <= 0;
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size_r <= size_r - 1;
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end
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end
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bypass_r <= writing
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&& (empty_r || ((1 == size_r) && reading)); // empty or about to go empty
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curr_r <= data_in;
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head_r <= data[reading ? rd_ptr_next_r : rd_ptr_r];
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end
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end
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assign data_out = bypass_r ? curr_r : head_r;
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assign empty = empty_r;
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assign full = full_r;
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assign size = size_r;
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end
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end
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endmodule |