76 lines
3.4 KiB
Verilog
76 lines
3.4 KiB
Verilog
`include "VX_define.vh"
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module VX_writeback #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_commit_if alu_commit_if,
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VX_commit_if lsu_commit_if,
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VX_commit_if mul_commit_if,
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VX_commit_if csr_commit_if,
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// outputs
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VX_wb_if writeback_if
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);
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wire lsu_valid = (| lsu_commit_if.valid) && (lsu_commit_if.wb != `WB_NO);
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wire mul_valid = (| mul_commit_if.valid) && (mul_commit_if.wb != `WB_NO);
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wire alu_valid = (| alu_commit_if.valid) && (alu_commit_if.wb != `WB_NO);
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wire csr_valid = (| csr_commit_if.valid) && (csr_commit_if.wb != `WB_NO);
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VX_wb_if writeback_tmp_if();
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assign writeback_tmp_if.valid = lsu_valid ? lsu_commit_if.valid :
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mul_valid ? mul_commit_if.valid :
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alu_valid ? alu_commit_if.valid :
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csr_valid ? csr_commit_if.valid :
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0;
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assign writeback_tmp_if.warp_num = lsu_valid ? lsu_commit_if.warp_num :
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mul_valid ? mul_commit_if.warp_num :
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alu_valid ? alu_commit_if.warp_num :
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csr_valid ? csr_commit_if.warp_num :
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0;
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assign writeback_tmp_if.data = lsu_valid ? lsu_commit_if.data :
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mul_valid ? mul_commit_if.data :
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alu_valid ? alu_commit_if.data :
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csr_valid ? csr_commit_if.data :
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0;
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assign writeback_tmp_if.rd = lsu_valid ? lsu_commit_if.rd :
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mul_valid ? mul_commit_if.rd :
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alu_valid ? alu_commit_if.rd :
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csr_valid ? csr_commit_if.rd :
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0;
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wire stall = ~writeback_if.ready && (| writeback_if.valid);
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VX_generic_register #(
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.N(`NUM_THREADS + `NW_BITS + `NR_BITS + (`NUM_THREADS * 32))
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) wb_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (0),
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.in ({writeback_tmp_if.valid, writeback_tmp_if.warp_num, writeback_tmp_if.rd, writeback_tmp_if.data}),
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.out ({writeback_if.valid, writeback_if.warp_num, writeback_if.rd, writeback_if.data})
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);
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assign lsu_commit_if.ready = !stall;
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assign mul_commit_if.ready = !stall && !lsu_valid;
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assign alu_commit_if.ready = !stall && !lsu_valid && !mul_valid;
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assign csr_commit_if.ready = !stall && !lsu_valid && !mul_valid && !alu_valid;
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// special workaround to control RISC-V benchmarks termination on Verilator
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reg [31:0] last_data_wb /* verilator public */;
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always @(posedge clk) begin
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if ((| writeback_tmp_if.valid) && ~stall && (writeback_tmp_if.rd == 28)) begin
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last_data_wb <= writeback_tmp_if.data[0];
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end
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end
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endmodule |