88 lines
3.4 KiB
Verilog
88 lines
3.4 KiB
Verilog
`include "VX_define.vh"
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module VX_scheduler #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_decode_if decode_if,
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VX_wb_if writeback_if,
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input wire alu_busy,
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input wire lsu_busy,
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input wire csr_busy,
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input wire mul_busy,
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input wire gpu_busy,
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output wire schedule_delay,
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output wire is_empty
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);
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localparam CTVW = `CLOG2(`NUM_WARPS * 32 + 1);
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reg [31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0];
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reg [CTVW-1:0] count_valid;
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wire rs1_rename = (rename_table[decode_if.warp_num][decode_if.rs1] != 0);
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wire rs2_rename = (rename_table[decode_if.warp_num][decode_if.rs2] != 0);
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wire rd_rename = (rename_table[decode_if.warp_num][decode_if.rd ] != 0);
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wire rs1_rename_qual = (rs1_rename) && (decode_if.use_rs1);
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wire rs2_rename_qual = (rs2_rename) && (decode_if.use_rs2);
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wire rd_rename_qual = (rd_rename) && (decode_if.wb != 0);
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wire rename_valid = (| decode_if.valid) && (rs1_rename_qual || rs2_rename_qual || rd_rename_qual);
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wire ex_stalled = (| decode_if.valid)
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&& ((alu_busy && (decode_if.ex_type == `EX_ALU))
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|| (lsu_busy && (decode_if.ex_type == `EX_LSU))
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|| (csr_busy && (decode_if.ex_type == `EX_CSR))
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|| (mul_busy && (decode_if.ex_type == `EX_MUL))
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|| (gpu_busy && (decode_if.ex_type == `EX_GPU)));
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wire stall = ex_stalled || rename_valid;
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wire acquire_rd = (| decode_if.valid) && (decode_if.wb != 0) && ~stall;
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wire release_rd = (| writeback_if.valid);
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wire [`NUM_THREADS-1:0] valid_wb_new_mask = rename_table[writeback_if.warp_num][writeback_if.rd] & ~writeback_if.valid;
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reg [CTVW-1:0] count_valid_next = (acquire_rd && !(release_rd && (0 == valid_wb_new_mask))) ? (count_valid + 1) :
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(~acquire_rd && (release_rd && (0 == valid_wb_new_mask))) ? (count_valid - 1) :
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count_valid;
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integer i, w;
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always @(posedge clk) begin
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if (reset) begin
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for (w = 0; w < `NUM_WARPS; w++) begin
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for (i = 0; i < 32; i++) begin
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rename_table[w][i] <= 0;
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end
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end
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count_valid <= 0;
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end else begin
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if (acquire_rd) begin
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rename_table[decode_if.warp_num][decode_if.rd] <= decode_if.valid;
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end
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if (release_rd) begin
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assert(rename_table[writeback_if.warp_num][writeback_if.rd] != 0);
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rename_table[writeback_if.warp_num][writeback_if.rd] <= valid_wb_new_mask;
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end
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count_valid <= count_valid_next;
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end
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end
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assign decode_if.ready = ~stall;
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assign schedule_delay = stall;
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assign is_empty = (0 == count_valid);
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (stall) begin
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$display("%t: Core%0d-stall: warp=%0d, PC=%0h, rd=%0d, wb=%0d, rename=%b%b%b, alu=%b, lsu=%b, csr=%b, mul=%b, gpu=%b", $time, CORE_ID, decode_if.warp_num, decode_if.curr_PC, decode_if.rd, decode_if.wb, rd_rename_qual, rs1_rename_qual, rs2_rename_qual, alu_busy, lsu_busy, csr_busy, mul_busy, gpu_busy);
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end
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end
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`endif
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endmodule |