155 lines
7.9 KiB
Verilog
155 lines
7.9 KiB
Verilog
`include "VX_define.vh"
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module VX_issue #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_decode_if decode_if,
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VX_wb_if writeback_if,
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VX_alu_req_if alu_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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VX_gpu_req_if gpu_req_if
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);
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VX_gpr_data_if gpr_data_if();
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wire schedule_delay;
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wire alu_busy = ~alu_req_if.ready/* && (| alu_req_if.valid)*/;
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wire lsu_busy = ~lsu_req_if.ready/* && (| lsu_req_if.valid)*/;
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wire csr_busy = ~csr_req_if.ready/* && (| csr_req_if.valid)*/;
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wire mul_busy = ~mul_req_if.ready/* && (| mul_req_if.valid)*/;
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wire gpu_busy = ~gpu_req_if.ready/* && (| gpu_req_if.valid)*/;
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VX_scheduler #(
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.CORE_ID(CORE_ID)
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) scheduler (
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.clk (clk),
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.reset (reset),
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.decode_if (decode_if),
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.writeback_if (writeback_if),
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.alu_busy (alu_busy),
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.lsu_busy (lsu_busy),
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.csr_busy (csr_busy),
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.mul_busy (mul_busy),
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.gpu_busy (gpu_busy),
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.schedule_delay (schedule_delay),
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`UNUSED_PIN (is_empty)
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);
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VX_gpr_stage #(
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.CORE_ID(CORE_ID)
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) gpr_stage (
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.clk (clk),
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.decode_if (decode_if),
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.writeback_if (writeback_if),
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.gpr_data_if (gpr_data_if)
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);
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VX_alu_req_if alu_req_tmp_if();
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VX_lsu_req_if lsu_req_tmp_if();
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VX_csr_req_if csr_req_tmp_if();
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VX_mul_req_if mul_req_tmp_if();
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VX_gpu_req_if gpu_req_tmp_if();
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VX_issue_mux issue_mux (
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.decode_if (decode_if),
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.gpr_data_if (gpr_data_if),
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.alu_req_if (alu_req_tmp_if),
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.lsu_req_if (lsu_req_tmp_if),
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.csr_req_if (csr_req_tmp_if),
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.mul_req_if (mul_req_tmp_if),
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.gpu_req_if (gpu_req_tmp_if)
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);
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wire stall_alu = ~alu_req_if.ready || schedule_delay;
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wire stall_lsu = ~lsu_req_if.ready || schedule_delay;
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wire stall_csr = ~csr_req_if.ready || schedule_delay;
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wire stall_mul = ~mul_req_if.ready || schedule_delay;
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wire stall_gpu = ~gpu_req_if.ready || schedule_delay;
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wire flush_alu = alu_req_if.ready && schedule_delay;
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wire flush_lsu = lsu_req_if.ready && schedule_delay;
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wire flush_csr = csr_req_if.ready && schedule_delay;
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wire flush_mul = mul_req_if.ready && schedule_delay;
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wire flush_gpu = gpu_req_if.ready && schedule_delay;
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VX_generic_register #(
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.N(`NUM_THREADS +`NW_BITS + 32 + `ALU_BITS + `WB_BITS + `NR_BITS + (`NUM_THREADS * 32) + (`NUM_THREADS * 32) + 32 + 32)
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) alu_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall_alu),
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.flush (flush_alu),
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.in ({alu_req_tmp_if.valid, alu_req_tmp_if.warp_num, alu_req_tmp_if.curr_PC, alu_req_tmp_if.alu_op, alu_req_tmp_if.wb, alu_req_tmp_if.rd, alu_req_tmp_if.rs1_data, alu_req_tmp_if.rs2_data, alu_req_tmp_if.offset, alu_req_tmp_if.next_PC}),
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.out ({alu_req_if.valid, alu_req_if.warp_num, alu_req_if.curr_PC, alu_req_if.alu_op, alu_req_if.wb, alu_req_if.rd, alu_req_if.rs1_data, alu_req_if.rs2_data, alu_req_if.offset, alu_req_if.next_PC})
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);
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VX_generic_register #(
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.N(`NUM_THREADS + `NW_BITS + 32 + 1 + `BYTEEN_BITS + `WB_BITS + `NR_BITS + (`NUM_THREADS * 32) + (`NUM_THREADS * 32) + 32)
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) lsu_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall_lsu),
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.flush (flush_lsu),
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.in ({lsu_req_tmp_if.valid, lsu_req_tmp_if.warp_num, lsu_req_tmp_if.curr_PC, lsu_req_tmp_if.rw, lsu_req_tmp_if.byteen, lsu_req_tmp_if.wb, lsu_req_tmp_if.rd, lsu_req_tmp_if.base_addr, lsu_req_tmp_if.offset, lsu_req_tmp_if.store_data}),
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.out ({lsu_req_if.valid, lsu_req_if.warp_num, lsu_req_if.curr_PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.wb, lsu_req_if.rd, lsu_req_if.base_addr, lsu_req_if.offset, lsu_req_if.store_data})
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);
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VX_generic_register #(
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.N(`NUM_THREADS + `NW_BITS + 32 + `CSR_BITS + `WB_BITS + `NR_BITS + `CSR_ADDR_SIZE + 32 + 1)
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) csr_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall_csr),
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.flush (flush_csr),
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.in ({csr_req_tmp_if.valid, csr_req_tmp_if.warp_num, csr_req_tmp_if.curr_PC, csr_req_tmp_if.csr_op, csr_req_tmp_if.wb, csr_req_tmp_if.rd, csr_req_tmp_if.csr_addr, csr_req_tmp_if.csr_mask, csr_req_tmp_if.is_io}),
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.out ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.curr_PC, csr_req_if.csr_op, csr_req_if.wb, csr_req_if.rd, csr_req_if.csr_addr, csr_req_if.csr_mask, csr_req_if.is_io})
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);
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VX_generic_register #(
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.N(`NUM_THREADS +`NW_BITS + 32 + `MUL_BITS + `WB_BITS + `NR_BITS + (`NUM_THREADS * 32) + (`NUM_THREADS * 32))
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) mul_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall_mul),
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.flush (flush_mul),
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.in ({mul_req_tmp_if.valid, mul_req_tmp_if.warp_num, mul_req_tmp_if.curr_PC, mul_req_tmp_if.mul_op, mul_req_tmp_if.wb, mul_req_tmp_if.rd, mul_req_tmp_if.rs1_data, mul_req_tmp_if.rs2_data}),
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.out ({mul_req_if.valid, mul_req_if.warp_num, mul_req_if.curr_PC, mul_req_if.mul_op, mul_req_if.wb, mul_req_if.rd, mul_req_if.rs1_data, mul_req_if.rs2_data})
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);
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VX_generic_register #(
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.N(`NUM_THREADS + `NW_BITS + 32 + `GPU_BITS + (`NUM_THREADS * 32) + 32 + 32)
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) gpu_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall_gpu),
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.flush (flush_gpu),
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.in ({gpu_req_tmp_if.valid, gpu_req_tmp_if.warp_num, gpu_req_tmp_if.curr_PC, gpu_req_tmp_if.gpu_op, gpu_req_tmp_if.rs1_data, gpu_req_tmp_if.rs2_data, gpu_req_tmp_if.next_PC}),
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.out ({gpu_req_if.valid, gpu_req_if.warp_num, gpu_req_if.curr_PC, gpu_req_if.gpu_op, gpu_req_if.rs1_data, gpu_req_if.rs2_data, gpu_req_if.next_PC})
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);
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if ((| alu_req_tmp_if.valid) && ~stall_alu) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=ALU, op=%0d, wb=%d, rd=%0d, rs1=%0h, rs2=%0h, offset=%0h, next_PC=%0h", $time, CORE_ID, alu_req_tmp_if.warp_num, alu_req_tmp_if.curr_PC, alu_req_tmp_if.alu_op, alu_req_tmp_if.wb, alu_req_tmp_if.rd, alu_req_tmp_if.rs1_data, alu_req_tmp_if.rs2_data, alu_req_tmp_if.offset, alu_req_tmp_if.next_PC);
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end
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if ((| mul_req_tmp_if.valid) && ~stall_mul) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=MUL, op=%0d, wb=%d, rd=%0d, rs1=%0h, rs2=%0h", $time, CORE_ID, mul_req_tmp_if.warp_num, mul_req_tmp_if.curr_PC, mul_req_tmp_if.mul_op, mul_req_tmp_if.wb, mul_req_tmp_if.rd, mul_req_tmp_if.rs1_data, mul_req_tmp_if.rs2_data);
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end
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if ((| lsu_req_tmp_if.valid) && ~stall_lsu) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=LSU, rw=%b, wb=%0d, rd=%0d, byteen=%b, baddr=%0h, offset=%0h", $time, CORE_ID, lsu_req_tmp_if.warp_num, lsu_req_tmp_if.curr_PC, lsu_req_tmp_if.rw, lsu_req_tmp_if.rd, lsu_req_tmp_if.wb, lsu_req_tmp_if.byteen, lsu_req_tmp_if.base_addr, lsu_req_tmp_if.offset);
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end
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if ((| csr_req_tmp_if.valid) && ~stall_csr) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=CSR, op=%0d, wb=%d, rd=%0d, addr=%0h, mask=%0h", $time, CORE_ID, csr_req_tmp_if.warp_num, csr_req_tmp_if.curr_PC, csr_req_tmp_if.csr_op, csr_req_tmp_if.wb, csr_req_tmp_if.rd, csr_req_tmp_if.csr_addr, csr_req_tmp_if.csr_mask);
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end
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if ((| gpu_req_tmp_if.valid) && ~stall_gpu) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=GPU, op=%0d, rs1=%0h, rs2=%0h", $time, CORE_ID, gpu_req_tmp_if.warp_num, gpu_req_tmp_if.curr_PC, gpu_req_tmp_if.gpu_op, gpu_req_tmp_if.rs1_data, gpu_req_tmp_if.rs2_data);
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end
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end
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`endif
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endmodule |