54 lines
1.9 KiB
Verilog
54 lines
1.9 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_data #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire[`CSR_ADDR_SIZE-1:0] read_addr,
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output reg[31:0] read_data,
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input wire write_enable,
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`IGNORE_WARNINGS_BEGIN
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// We use a smaller storage for CSRs than the standard 4KB in RISC-V
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input wire[`CSR_ADDR_SIZE-1:0] write_addr,
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`IGNORE_WARNINGS_END
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input wire[`CSR_WIDTH-1:0] write_data,
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input wire[`NW_BITS-1:0] warp_num,
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VX_perf_cntrs_if perf_cntrs_if
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);
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reg [`CSR_WIDTH-1:0] csr_table[`NUM_CSRS-1:0];
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// cast address to physical CSR range
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wire [$clog2(`NUM_CSRS)-1:0] rd_addr, wr_addr;
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assign rd_addr = $size(rd_addr)'(read_addr);
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assign wr_addr = $size(wr_addr)'(write_addr);
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always @(posedge clk) begin
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if (write_enable) begin
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csr_table[wr_addr] <= write_data;
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end
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end
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always @(*) begin
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case (read_addr)
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`CSR_LWID : read_data = 32'(warp_num);
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`CSR_GTID ,
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`CSR_GWID : read_data = CORE_ID * `NUM_WARPS + 32'(warp_num);
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`CSR_GCID : read_data = CORE_ID;
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`CSR_NT : read_data = `NUM_THREADS;
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`CSR_NW : read_data = `NUM_WARPS;
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`CSR_NC : read_data = `NUM_CORES * `NUM_CLUSTERS;
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`CSR_CYCLE_L : read_data = perf_cntrs_if.total_cycles[31:0];
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`CSR_CYCLE_H : read_data = perf_cntrs_if.total_cycles[63:32];
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`CSR_INSTR_L : read_data = perf_cntrs_if.total_instrs[31:0];
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`CSR_INSTR_H : read_data = perf_cntrs_if.total_instrs[63:32];
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`CSR_VEND_ID : read_data = `VENDOR_ID;
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`CSR_ARCH_ID : read_data = `ARCHITECTURE_ID;
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`CSR_IMPL_ID : read_data = `IMPLEMENTATION_ID;
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`CSR_MISA : read_data = `ISA_CODE;
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default : read_data = 32'(csr_table[rd_addr]);
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endcase
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end
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endmodule
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