d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
61 lines
1.7 KiB
Systemverilog
61 lines
1.7 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_sp_ram #(
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter WRENW = 1,
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parameter OUT_REG = 0,
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parameter NO_RWCHECK = 0,
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parameter LUTRAM = 0,
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parameter INIT_ENABLE = 0,
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parameter INIT_FILE = "",
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parameter [DATAW-1:0] INIT_VALUE = 0,
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parameter ADDRW = `LOG2UP(SIZE)
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) (
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input wire clk,
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input wire read,
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input wire write,
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input wire [WRENW-1:0] wren,
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input wire [ADDRW-1:0] addr,
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input wire [DATAW-1:0] wdata,
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output wire [DATAW-1:0] rdata
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);
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VX_dp_ram #(
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.DATAW (DATAW),
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.SIZE (SIZE),
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.WRENW (WRENW),
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.OUT_REG (OUT_REG),
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.NO_RWCHECK (NO_RWCHECK),
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.LUTRAM (LUTRAM),
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.INIT_ENABLE (INIT_ENABLE),
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.INIT_FILE (INIT_FILE),
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.INIT_VALUE (INIT_VALUE),
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.ADDRW (ADDRW)
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) dp_ram (
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.clk (clk),
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.read (read),
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.write (write),
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.wren (wren),
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.waddr (addr),
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.wdata (wdata),
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.raddr (addr),
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.rdata (rdata)
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);
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endmodule
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`TRACING_ON
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