Blaise Tine d956e268b9 adding new performance counters (banks utilization and DRAM bus utilization)

2020-12-22 12:33:45 -08:00

..

configs

project directories reorganization

2020-04-14 06:35:20 -04:00

models/memory

RTL code refactoring

2020-04-19 03:38:00 -04:00

modelsim

yosys synthesis refactoring

2020-07-10 18:56:41 -04:00

old_rtl

refactoring fixes

2020-04-14 19:39:59 -04:00

opae

performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00

rtl

adding new performance counters (banks utilization and DRAM bus utilization)

2020-12-22 12:33:45 -08:00

scripts

performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00

simulate

adding new performance counters (banks utilization and DRAM bus utilization)

2020-12-22 12:33:45 -08:00

syn

allowing partial cache request submissions, io bus support broken

2020-12-21 03:53:13 -08:00

unit_tests

rename MSRQ to MSHR

2020-11-28 17:32:00 -05:00

.gitignore

adding dram writeenable support + scheduler bug fixes

2020-05-27 19:00:23 -04:00

Makefile

scope refactoring

2020-10-03 18:53:21 -04:00