24 lines
424 B
Verilog
24 lines
424 B
Verilog
`ifndef VX_MUL_REQ_IF
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`define VX_MUL_REQ_IF
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`include "VX_define.vh"
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`ifndef EXT_M_ENABLE
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`IGNORE_WARNINGS_BEGIN
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`endif
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interface VX_mul_req_if ();
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wire valid;
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wire [`ISTAG_BITS-1:0] issue_tag;
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wire [`MUL_BITS-1:0] mul_op;
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wire [`NUM_THREADS-1:0][31:0] rs1_data;
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wire [`NUM_THREADS-1:0][31:0] rs2_data;
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wire ready;
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endinterface
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`endif |